| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | Add "rename -output" | Clifford Wolf | 2019-03-27 | 1 | -3/+23 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Improve "rename" help message | Clifford Wolf | 2019-03-27 | 1 | -0/+6 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add "cutpoint -undef" | Clifford Wolf | 2019-03-26 | 1 | -10/+14 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 2 | -0/+5 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 2 | -15/+93 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | synth_xilinx to use shregmap with -minlen 3 | Eddie Hung | 2019-03-25 | 1 | -2/+2 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-25 | 15 | -37/+943 | |
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| | * | | | Add "cutpoint" pass | Clifford Wolf | 2019-03-25 | 2 | -0/+165 | |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge pull request #896 from YosysHQ/transp_fixes | Clifford Wolf | 2019-03-25 | 1 | -9/+16 | |
| | |\ \ | | | | | | | | | memory_bram: Fix multiclock make_transp | |||||
| | | * | | memory_bram: Fix multiclock make_transp | David Shah | 2019-03-24 | 1 | -9/+16 | |
| | | |/ | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | Merge pull request #897 from trcwm/libertyfixes | Clifford Wolf | 2019-03-25 | 8 | -22/+645 | |
| | |\ \ | | |/ | |/| | Liberty parser: Accept ranges [A:B], and ignore missing ';'. | |||||
| | | * | spaces -> tabs | Niels Moseley | 2019-03-25 | 1 | -78/+78 | |
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| | | * | EOL is now accepted as ';' replacement on lines that look like: ↵ | Niels Moseley | 2019-03-25 | 1 | -4/+3 | |
| | | | | | | | | | | | | | feature_xyz(option) | |||||
| | | * | Updated the liberty parser to accept [A:B] ranges (AST has not been ↵ | Niels Moseley | 2019-03-24 | 8 | -7/+631 | |
| | |/ | | | | | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. | |||||
| | * | Add "mutate -none -mode", "mutate -mode none" | Clifford Wolf | 2019-03-23 | 1 | -1/+30 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add "mutate -s <filename>" | Clifford Wolf | 2019-03-23 | 1 | -2/+24 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #893 from YosysHQ/clifford/btormeminit | Clifford Wolf | 2019-03-23 | 3 | -3/+63 | |
| | |\ | | | | | | | Memory init support in write_btor | |||||
| | | * | Add support for memory initialization to write_btor | Clifford Wolf | 2019-03-23 | 1 | -0/+53 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix BTOR output tags syntax in writye_btor | Clifford Wolf | 2019-03-23 | 1 | -2/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals | Clifford Wolf | 2019-03-23 | 2 | -1/+9 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Cope with SHREG not having E port; Revert $pmux fine tune | Eddie Hung | 2019-03-23 | 1 | -4/+3 | |
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| * | | Add support for SHREGMAP+$mux, also fine tune $pmux | Eddie Hung | 2019-03-22 | 1 | -1/+24 | |
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| * | | Leftover printf | Eddie Hung | 2019-03-22 | 1 | -1/+0 | |
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| * | | Fixes for multibit | Eddie Hung | 2019-03-22 | 1 | -18/+38 | |
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| * | | Working for 1 bit | Eddie Hung | 2019-03-22 | 1 | -11/+49 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-22 | 7 | -44/+115 | |
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| | * | Merge pull request #889 from YosysHQ/clifford/fix888 | Clifford Wolf | 2019-03-22 | 1 | -1/+10 | |
| | |\ | | | | | | | Fix mem2reg handling of memories with upto data ports | |||||
| | | * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge pull request #890 from YosysHQ/clifford/fix887 | Clifford Wolf | 2019-03-22 | 1 | -1/+26 | |
| | |\ \ | | | | | | | | | Trim init attributes when resizing FFs in "wreduce" | |||||
| | | * | | Trim init attributes when resizing FFs in "wreduce", fixes #887 | Clifford Wolf | 2019-03-22 | 1 | -1/+26 | |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge pull request #891 from YosysHQ/xilinx_keep | David Shah | 2019-03-22 | 2 | -25/+31 | |
| | |\ \ | | |/ | |/| | xilinx: Add keep attribute where appropriate | |||||
| | | * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 | |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 3 | -15/+42 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 | |
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| * | | Opt | Eddie Hung | 2019-03-21 | 1 | -1/+1 | |
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| * | | Fix spacing | Eddie Hung | 2019-03-20 | 1 | -239/+239 | |
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| * | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 | |
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| * | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 2 | -58/+34 | |
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| * | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 2 | -17/+67 | |
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| * | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 | |
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| * | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| * | | shregmap -tech xilinx to delete $shiftx for var length SRL | Eddie Hung | 2019-03-19 | 1 | -10/+3 | |
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| * | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 53 | -38/+2398 | |
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| | * | Merge pull request #885 from YosysHQ/clifford/fix873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| | |\ | | | | | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | |||||
| | | * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #808 from eddiehung/read_aiger | Eddie Hung | 2019-03-19 | 35 | -6/+632 | |
| | |\ | | | | | | | Add new read_aiger frontend | |||||
| | | * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 113 | -792/+6364 | |
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| | * | | Merge pull request #884 from zachjs/master | Clifford Wolf | 2019-03-19 | 2 | -1/+61 | |
| | |\ \ | | | | | | | | | fix local name resolution in prefix constructs | |||||
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index : iCE40/yosys | |
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