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* | Removed "make mklibyosys"Clifford Wolf2015-02-071-14/+0
* | Improved building of pluginsClifford Wolf2015-02-072-3/+36
* | Added "make uninstall"Clifford Wolf2015-02-071-0/+4
* | Added cell->known(), cell->input(portname), cell->output(portname)Clifford Wolf2015-02-072-0/+39
* | Added "select -read"Clifford Wolf2015-02-061-5/+39
* | Auto-detect TCL versionClifford Wolf2015-02-052-2/+2
* | Added onehot attributeClifford Wolf2015-02-043-0/+19
* | Fixed opt_clean performance bugClifford Wolf2015-02-041-26/+26
* | Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
* | Using design->selected_modules() in opt_*Clifford Wolf2015-02-035-36/+20
* | Skip blackbox modules in design->selected_modules()Clifford Wolf2015-02-031-3/+5
* | Added "yosys -L logfile"Clifford Wolf2015-02-031-1/+7
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-02-012-3/+3
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| * \ Merge pull request #48 from rubund/masterClifford Wolf2015-02-012-3/+3
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| | * | Fixed typos found by lintianRuben Undheim2015-02-012-3/+3
* | | | no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
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* / / Improved performance in equiv_simpleClifford Wolf2015-02-012-23/+73
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* | Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
* | Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
* | Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-011-11/+10
* | Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
* | Added "make mklibyosys", some minor API changesClifford Wolf2015-02-017-11/+70
* | Minor README changesClifford Wolf2015-02-011-3/+2
* | Removed TODO list from README fileClifford Wolf2015-02-011-30/+0
* | Added yosys_banner(), Updated Copyright rangeClifford Wolf2015-02-014-26/+31
* | Added <algorithm> include to hashlib.hClifford Wolf2015-02-011-0/+1
* | Using selections in "ls" commandClifford Wolf2015-02-011-34/+30
* | Shorter "dump" optionsClifford Wolf2015-01-311-4/+4
* | Bugfix in opt_const $eq -> buffer codeClifford Wolf2015-01-311-4/+4
* | Log msg changeClifford Wolf2015-01-311-1/+1
* | Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")Clifford Wolf2015-01-311-12/+31
* | Added "equiv_induct -undef"Clifford Wolf2015-01-312-6/+51
* | Added "equiv_simple -undef"Clifford Wolf2015-01-312-17/+61
* | Added "equiv_make -blacklist <file> -encfile <file>"Clifford Wolf2015-01-314-5/+189
* | Synced RTLIL::unescape_id() to log_id() behaviorClifford Wolf2015-01-301-3/+9
* | Added "fsm -encfile"Clifford Wolf2015-01-303-14/+50
* | More log_id() stuffClifford Wolf2015-01-301-3/+7
* | Some cleanups in log.ccClifford Wolf2015-01-301-14/+16
* | Improved an error messageClifford Wolf2015-01-281-1/+1
* | Fixed bug in equiv_miterClifford Wolf2015-01-281-6/+6
* | Added "sat -show-ports"Clifford Wolf2015-01-271-2/+7
* | Bugfix in resource sharing testClifford Wolf2015-01-271-1/+1
* | Updaed ABC to hg rev 61ad5f908c03Clifford Wolf2015-01-271-1/+1
* | Rethrow with "catch(...) throw;"Clifford Wolf2015-01-253-6/+6
* | Added equiv_removeClifford Wolf2015-01-252-0/+84
* | Added equiv_miterClifford Wolf2015-01-252-0/+344
* | Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-2412-12/+33
* | Added #ifdef NDEBUG for log_assert()Clifford Wolf2015-01-241-1/+5
* | Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
* | Various equiv_* improvementsClifford Wolf2015-01-244-14/+20