| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 |
| | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. | ||||
| * | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
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| * | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 |
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| * | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
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| * | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -18/+167 |
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| * | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 |
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| * | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 |
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| * | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 |
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| * | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 |
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| * | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 |
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| * | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 |
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| * | Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -0/+17 |
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| | * | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 |
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| * | | Add init support | Eddie Hung | 2019-08-21 | 2 | -3/+12 |
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| * | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 |
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| * | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 |
| |\ | | | | | techmap -max_iter to apply to each module individually | ||||
| | * | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| | * | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 |
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| | * | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 |
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| * | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 |
| |\ | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 |
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| | * | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 |
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| | * | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 |
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| | * | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| | * | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 |
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| | * | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
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| * | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 |
| |\ \ \ | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | ||||
| | * | | | Clarify with 'only' | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| | * | | | Update doc | Eddie Hung | 2019-08-19 | 1 | -3/+4 |
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| | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 4 | -12/+12 |
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| | * | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 |
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| | * | | | Add doc for abc_* attributes | Eddie Hung | 2019-08-16 | 1 | -0/+16 |
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| | * | | | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 2 | -11/+21 |
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| | * | | | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 2 | -85/+80 |
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| | * | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| * | | | | Merge pull request #1298 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-20 | 12 | -93/+790 |
| |\ \ \ \ | | | | | | | | | | | Improvements in pmgen | ||||
| | * \ \ \ | Merge branch 'master' into clifford/pmgen | Clifford Wolf | 2019-08-20 | 13 | -39/+85 |
| | |\ \ \ \ | |/ / / / |/| | | | | |||||
| * | | | | | Add test case for real parameters | Clifford Wolf | 2019-08-20 | 1 | -1/+10 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Merge pull request #1308 from jakobwenzel/real_params | Clifford Wolf | 2019-08-20 | 1 | -1/+4 |
| |\ \ \ \ \ | | | | | | | | | | | | | Handle real values when deriving ast modules | ||||
| | * | | | | | handle real values when deriving ast modules | Jakob Wenzel | 2019-08-19 | 1 | -1/+4 |
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| * | | | | | | Merge pull request #1309 from whitequark/proc_clean-fix-1268 | whitequark | 2019-08-20 | 6 | -2/+37 |
| |\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | | proc_clean: fix order of switch insertion | ||||
| | * | | | | | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 6 | -2/+37 |
| | |/ / / / | | | | | | | | | | | | | | | | Fixes #1268. | ||||
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index : iCE40/yosys | |
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