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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 15:56:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 15:56:57 -0700 |
| commit | 1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a (patch) | |
| tree | 0679a8bb92d581250c88b3b541f0bb18e56628a0 | |
| parent | 4fe307f1bc02e32ae70f7ef9495f3418303e43e9 (diff) | |
| download | yosys-1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a.tar.gz yosys-1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a.tar.bz2 yosys-1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a.zip | |
Update abc_* attr in ecp5 and ice40
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 22 | ||||
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 10 |
2 files changed, 21 insertions, 11 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 3d343b315..864a3550f 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z); endmodule // --------------------------------------- -(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) -module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, COUT); - +(* abc_box_id=1, lib_whitebox *) +module CCU2C( + (* abc_carry_in *) input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + (* abc_carry_out *) output COUT +); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; parameter INJECT1_0 = "YES"; @@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, WCK, - input [3:0] RAD, + (* abc_scc_break *) input [3:0] DI, + (* abc_scc_break *) input [3:0] WAD, + (* abc_scc_break *) input WRE, + input WCK, + input [3:0] RAD, output [3:0] DO ); parameter WCKMUX = "WCK"; diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..5b18fec27 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry_out *) output CO, + output O, + input A, + input B, + (* abc_carry_in *) input CI +); SB_CARRY carry ( .I0(A), .I1(B), |