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* Merge pull request #3684 from YosysHQ/fix-GIT_REVN. Engelhardt2023-03-061-1/+1
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| * Makefile: fix GIT_REV extraction if Yosys is built as submodule.Catherine2023-03-011-1/+1
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* | Next dev cycleMiodrag Milanovic2023-03-062-2/+5
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* | Release version 0.27Miodrag Milanovic2023-03-062-3/+14
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* | Bump versiongithub-actions[bot]2023-03-021-1/+1
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* | Merge pull request #3690 from whitequark/smtbmc-help-optN. Engelhardt2023-03-011-4/+13
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| * | yosys-smtbmc: support -h/--help (and exit with code 0).Catherine2023-02-271-4/+13
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* | | Merge pull request #3692 from nakengelhardt/stat_q_fixN. Engelhardt2023-03-011-1/+1
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| * | | stat: pass down quiet argN. Engelhardt2023-02-281-1/+1
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* | | | Merge pull request #3688 from pu-cc/gatemate-reginitN. Engelhardt2023-03-013-8/+16
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| * | | gatemate: Enable register initializationPatrick Urban2023-02-153-8/+16
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* | | | Merge pull request #3663 from uis246/masterMiodrag Milanović2023-02-281-0/+17
|\ \ \ \ | | | | | | | | | | gowin: Add new types of oscillator
| * | | | gowin: Add new types of oscillatoruis2023-02-061-0/+17
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* | | | | Merge pull request #3652 from martell/elvdsMiodrag Milanović2023-02-281-0/+8
|\ \ \ \ \ | | | | | | | | | | | | gowin: Add support for emulated differential output
| * | | | | gowin: Add support for emulated differential outputmartell2023-01-291-0/+8
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* | | | | Bump versiongithub-actions[bot]2023-02-281-1/+1
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* | | | | Merge pull request #3646 from YosysHQ/lofty/fix-3591Miodrag Milanović2023-02-272-4/+41
|\ \ \ \ \ | | | | | | | | | | | | muxcover: do not add decode muxes with x inputs
| * | | | | muxcover: do not add decode muxes with x inputsLofty2023-01-262-4/+41
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* | | | | | Merge pull request #3674 from YosysHQ/fix_wide_caseN. Engelhardt2023-02-278-14/+123
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| * | | | | | run verific tests in test targetMiodrag Milanovic2023-02-271-0/+3
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| * | | | | | Added ranged case checkMiodrag Milanovic2023-02-272-0/+27
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| * | | | | | Add test exampleMiodrag Milanovic2023-02-274-0/+51
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| * | | | | | Handle more wide case selector typesMiodrag Milanovic2023-02-271-14/+42
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* | | | | | | fabulous: Add support for mapping carry chainsgatecat2023-02-275-2/+102
|/ / / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | / / Bump versiongithub-actions[bot]2023-02-241-1/+1
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* | | | | Merge pull request #3685 from YosysHQ/update-abcCatherine2023-02-231-1/+1
|\ \ \ \ \ | |_|_|_|/ |/| | | | Update abc
| * | | | Update abc.Catherine2023-02-231-1/+1
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* | | | Bump versiongithub-actions[bot]2023-02-211-1/+1
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* | | | Merge pull request #3403 from KrystalDelusion/mem-testsN. Engelhardt2023-02-2026-14/+1696
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| * | | | Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
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| * | | | bug3205.ys removedKrystalDelusion2023-02-211-57/+0
| | | | | | | | | | | | | | | | | | | | Made redundant by TDP test(s) in memories.ys
| * | | | Removing extra `default_nettype` linesKrystalDelusion2023-02-211-2/+0
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| * | | | Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | Explicitly declare -top in synth_intel_alm.
| * | | | More tests in memlib/generate.pyKrystalDelusion2023-02-2113-12/+1180
| | | | | | | | | | | | | | | | | | | | Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
| * | | | Tests for ram_style = "huge"KrystalDelusion2023-02-214-0/+219
| | | | | | | | | | | | | | | | | | | | iCE40 SPRAM and Xilinx URAM
| * | | | Testing TDP synth mappingKrystalDelusion2023-02-213-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | New common sync_ram_tdp. Used in ecp5 and gatemate mem*.ys.
| * | | | Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
| | | | | | | | | | | | | | | | | | | | Uses verilog code from User Guide 901 (2021.1)
| * | | | Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
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* | | | Bump versiongithub-actions[bot]2023-02-181-1/+1
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* | | | Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dregN. Engelhardt2023-02-171-1/+1
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| * | | | Check DREG attributeOliver Keszöcze2023-02-171-1/+1
|/ / / / | | | | | | | | The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
* | | | Bump versiongithub-actions[bot]2023-02-171-1/+1
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* | | | fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Bump versiongithub-actions[bot]2023-02-161-1/+1
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* | | Merge pull request #3672 from jix/yw-cosim-hierarchy-fixesJannis Harder2023-02-151-1/+25
|\ \ \ | | | | | | | | sim: For yw cosim, drive parent module's signals for input ports
| * | | sim: For yw cosim, drive parent module's signals for input portsJannis Harder2023-02-131-1/+25
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* | | | Merge pull request #3675 from daglem/struct-item-queriesJannis Harder2023-02-152-12/+161
|\ \ \ \ | | | | | | | | | | Support for data and array queries on struct/union item expressions
| * | | | Corrected tests for data and array queries on struct/union item expressionsDag Lem2023-02-151-80/+85
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| * | | | Support for data and array queries on struct/union item expressionsDag Lem2023-02-152-12/+156
| | | | | | | | | | | | | | | | | | | | For now, $bits, $left, $right, $low, $high, and $size are supported.
* | | | | Merge pull request #3671 from zachjs/masterJannis Harder2023-02-152-0/+16
|\ \ \ \ \ | |/ / / / |/| | | | Add test for typenames using constants shadowed later on
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