iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
* \|	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	6	-22/+96
* \|	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	6	-2/+13
* \|	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	52	-251/+236
* \|	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	2	-0/+15
* \|	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
* \|	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
* \|	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28	2	-11/+17
* \|	Added techmap -extern	Clifford Wolf	2014-07-27	3	-17/+92
* \|	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	3	-4/+43
* \|	Added topological sorting to techmap	Clifford Wolf	2014-07-27	2	-21/+54
* \|	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	2	-2/+7
* \|	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27	1	-6/+7
* \|	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
* \|	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	2	-29/+157
* \|	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
* \|	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
* \|	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
* \|	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	4	-8/+7
* \|	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27	2	-55/+42
* \|	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27	1	-10/+10
* \|	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	10	-87/+85
* \|	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	2	-2/+20
* \|	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27	1	-0/+3
* \|	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	73	-223/+223
* \|	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
* \|	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	2	-7/+111
* \|	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27	1	-4/+4
* \|	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27	1	-0/+15
* \|	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27	1	-17/+57
* \|	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	61	-152/+152
* \|	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	50	-191/+191
* \|	New message for completion of build	Clifford Wolf	2014-07-26	1	-1/+1
* \|	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	8	-81/+52
* \|	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	19	-218/+150
* \|	Added tests/various/.gitignore	Clifford Wolf	2014-07-26	1	-0/+1
* \|	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26	3	-0/+28
* \|	Added support for here documents	Clifford Wolf	2014-07-26	3	-18/+63
* \|	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	5	-39/+39
* \|	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	12	-27/+33
* \|	Merge automatic and manual code changes for new cell connections API	Clifford Wolf	2014-07-26	61	-1201/+1247
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\| * \|	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	36	-123/+169
\| * \|	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	61	-1201/+1201
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* \|	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26	2	-9/+9
* \|	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26	2	-0/+6
* \|	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26	2	-0/+6
* \|	Use "wget -N" in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-26	1	-2/+2
* \|	Added "passed" message to make test targets	Clifford Wolf	2014-07-26	1	-0/+9
* \|	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26	2	-17/+63
* \|	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26	2	-0/+71