| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 34 | -361/+376 |
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| | * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 34 | -305/+313 |
| | * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 |
| | * | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
| | * | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 20 | -86/+374 |
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| | * | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 |
| | * | Update ABC to git rev 623b5e8 | Clifford Wolf | 2019-10-03 | 1 | -1/+1 |
| | * | Bump version | Clifford Wolf | 2019-10-03 | 1 | -1/+1 |
| | * | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 |
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| | | * | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
| | | * | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
| | * | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 2 | -6/+50 |
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| | | * | | Add quick test | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
| | | * | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 |
| | * | | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 2 | -27/+56 |
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| | | * | | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 |
| | | * | | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 2 | -21/+36 |
| | * | | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 | David Shah | 2019-10-03 | 6 | -2/+184 |
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| | | * | | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 |
| | | * | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 |
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| | * | | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire | Eddie Hung | 2019-10-02 | 2 | -0/+32 |
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| | | * | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 |
| | | * | | | | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 |
| | | * | | | | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
| | | * | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
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| | * | | | | log_dump() to support State enum | Eddie Hung | 2019-10-02 | 3 | -0/+6 |
| | * | | | | Merge pull request #1428 from YosysHQ/clifford/fixbtor | Clifford Wolf | 2019-10-02 | 1 | -6/+9 |
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| | | * | | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 |
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| | * | | | Merge pull request #1426 from YosysHQ/mmicko/fix_environ | Miodrag Milanović | 2019-10-01 | 1 | -0/+2 |
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| | | * | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 |
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| | * / | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
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| * | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 |
| * | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
| * | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
| * | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 2 | -13/+24 |
| * | | Resolve FIXME on calling proc just once | Eddie Hung | 2019-09-30 | 1 | -2/+2 |
| * | | Cleanup $currQ from aigerparse | Eddie Hung | 2019-09-30 | 1 | -2/+0 |
| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 4 | -114/+129 |
| * | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
| * | | Cleanup | Eddie Hung | 2019-09-30 | 1 | -100/+3 |
| * | | Add comment | Eddie Hung | 2019-09-30 | 1 | -0/+1 |
| * | | Use a cell_cache to instantiate once rather than opt_merge call | Eddie Hung | 2019-09-30 | 1 | -15/+15 |
| * | | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 2 | -29/+28 |
| * | | Use derived module | Eddie Hung | 2019-09-30 | 1 | -22/+5 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 29 | -132/+1981 |
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| | * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 |
| | * | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 11 | -0/+1767 |
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| | | * | rpc: new frontend. | whitequark | 2019-09-30 | 9 | -0/+744 |
| | | * | libs: import json11. | whitequark | 2019-09-30 | 3 | -0/+1023 |
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index : iCE40/yosys | |
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