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| * | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* / Update Verific default pathClifford Wolf2019-01-041-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #775 from whitequark/opt_flowmapClifford Wolf2019-01-033-1/+875
|\ | | | | flowmap: new techmap pass
| * flowmap: new techmap pass.whitequark2019-01-033-1/+875
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* | Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-023-97/+178
|\ \ | |/ |/| opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-022-70/+65
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-022-31/+42
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-022-32/+40
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-023-17/+84
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ \ | | | | | | anlogic: implement DRAM initialization
| * | anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2019-01-0211-35/+256
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| * \ \ Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-023-17/+45
| |\ \ \ | | | | | | | | | | Initialization of Anlogic DFFs
| | * | | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| | * | | Add "dffinit -noreinit" parameterIcenowy Zheng2018-12-181-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the FF cell might be initialized during the map process, e.g. some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has only a "SR" pin for a FF for async reset, that resets the FF to the initial value, which means the async reset value should be set as the initial value. In this case the DFFINIT pass shouldn't reinitialize it to a different value, which will lead to error. Add a "-noreinit" parameter for the safeguard. If a FF is not technically initialized before DFFINIT pass, the default value should be set to x. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| | * | | Add "dffinit -strinit high low"Icenowy Zheng2018-12-181-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms the string to initialize DFF might not be "high" and "low", e.g. with Anlogic TD it's "SET" and "RESET". Add a "-strinit" parameter for dffinit to allow specify the strings used for high and low. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * | | | Merge pull request #773 from whitequark/opt_lut_elim_fixesClifford Wolf2019-01-021-8/+31
| |\ \ \ \ | | | | | | | | | | | | opt_lut: elimination fixes
| | * | | | opt_lut: reflect changes in sigmap.whitequark2019-01-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Otherwise, some LUTs will be missed during elimination.
| | * | | | opt_lut: use a worklist, and revisit cells affected by elimination.whitequark2019-01-021-3/+10
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| | * | | | opt_lut: count eliminated cells, and set opt.did_something for them.whitequark2019-01-021-6/+20
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| * | | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
| |\ \ \ \ | | | | | | | | | | | | synth: add k-LUT mode
| | * | | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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| | * | | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| | * | | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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| * | | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-025-3/+139
| |\| | | | | | | | | | | | | | | | cmp2lut: new techmap pass
| | * | | | cmp2lut: new techmap pass.whitequark2019-01-025-3/+139
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* | / / / Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #769 from whitequark/typosClifford Wolf2019-01-0240-74/+74
|\ \ \ \ | |/ / / |/| | | Fix typographical and grammatical errors and inconsistencies
| * | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0240-74/+74
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | | Merge pull request #768 from whitequark/opt_lut_elimClifford Wolf2019-01-014-0/+104
|\ \ \ | | | | | | | | opt_lut: eliminate LUTs evaluating to constants or inputs
| * | | opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-314-0/+104
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* | | Fix handling of (* keep *) wires in wreduceClifford Wolf2018-12-311-1/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
|\ \ \ | | | | | | | | anlogic: add latch cells
| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| | |/ | |/| | | | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
| | | | | | | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
* | | Squelch a little more trailing whitespaceLarry Doolittle2018-12-292-4/+4
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* | | Merge pull request #761 from whitequark/proc_clean_partialClifford Wolf2018-12-233-10/+42
|\ \ \ | | | | | | | | proc_clean: remove any empty cases, if possible to do safely
| * | | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-233-6/+42
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| * | | proc_clean: remove any empty cases at the end of the switch.whitequark2018-12-221-7/+3
| | | | | | | | | | | | | | | | Previously, only completely empty switches were removed.
* | | | Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-12-237-22/+58
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| * \ \ \ Merge pull request #757 from whitequark/manual_memClifford Wolf2018-12-222-10/+37
| |\ \ \ \ | | |/ / / | |/| | | manual: document $meminit cell and memory_* passes
| | * | | manual: make description of $meminit ports match reality.whitequark2018-12-211-3/+15
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| | * | | manual: fix typos.whitequark2018-12-201-2/+2
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| | * | | manual: document $meminit cell and memory_* passes.whitequark2018-12-202-8/+23
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| * | | | Merge pull request #758 from whitequark/tcl_script_argsClifford Wolf2018-12-211-7/+18
| |\ \ \ \ | | | | | | | | | | | | tcl: add support for passing arguments to scripts
| | * | | | tcl: add support for passing arguments to scripts.whitequark2018-12-201-7/+18
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| * | | | Merge pull request #759 from whitequark/memory_collect_init_xClifford Wolf2018-12-211-3/+0
| |\ \ \ \ | | |/ / / | |/| | | memory_collect: do not truncate 'x from \INIT
| | * | | memory_collect: do not truncate 'x from \INIT.whitequark2018-12-211-3/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results.
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