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* Bump versiongithub-actions[bot]2023-02-281-1/+1
* Merge pull request #3646 from YosysHQ/lofty/fix-3591Miodrag Milanović2023-02-272-4/+41
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| * muxcover: do not add decode muxes with x inputsLofty2023-01-262-4/+41
* | Merge pull request #3674 from YosysHQ/fix_wide_caseN. Engelhardt2023-02-278-14/+123
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| * | run verific tests in test targetMiodrag Milanovic2023-02-271-0/+3
| * | Added ranged case checkMiodrag Milanovic2023-02-272-0/+27
| * | Add test exampleMiodrag Milanovic2023-02-274-0/+51
| * | Handle more wide case selector typesMiodrag Milanovic2023-02-271-14/+42
* | | fabulous: Add support for mapping carry chainsgatecat2023-02-275-2/+102
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* | Bump versiongithub-actions[bot]2023-02-241-1/+1
* | Merge pull request #3685 from YosysHQ/update-abcCatherine2023-02-231-1/+1
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| * | Update abc.Catherine2023-02-231-1/+1
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* | Bump versiongithub-actions[bot]2023-02-211-1/+1
* | Merge pull request #3403 from KrystalDelusion/mem-testsN. Engelhardt2023-02-2026-14/+1696
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| * | Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
| * | bug3205.ys removedKrystalDelusion2023-02-211-57/+0
| * | Removing extra `default_nettype` linesKrystalDelusion2023-02-211-2/+0
| * | Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
| * | More tests in memlib/generate.pyKrystalDelusion2023-02-2113-12/+1180
| * | Tests for ram_style = "huge"KrystalDelusion2023-02-214-0/+219
| * | Testing TDP synth mappingKrystalDelusion2023-02-213-0/+49
| * | Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
| * | Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
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* | Bump versiongithub-actions[bot]2023-02-181-1/+1
* | Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dregN. Engelhardt2023-02-171-1/+1
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| * | Check DREG attributeOliver Keszöcze2023-02-171-1/+1
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* | Bump versiongithub-actions[bot]2023-02-171-1/+1
* | fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
* | Bump versiongithub-actions[bot]2023-02-161-1/+1
* | Merge pull request #3672 from jix/yw-cosim-hierarchy-fixesJannis Harder2023-02-151-1/+25
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| * | sim: For yw cosim, drive parent module's signals for input portsJannis Harder2023-02-131-1/+25
* | | Merge pull request #3675 from daglem/struct-item-queriesJannis Harder2023-02-152-12/+161
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| * | | Corrected tests for data and array queries on struct/union item expressionsDag Lem2023-02-151-80/+85
| * | | Support for data and array queries on struct/union item expressionsDag Lem2023-02-152-12/+156
* | | | Merge pull request #3671 from zachjs/masterJannis Harder2023-02-152-0/+16
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| * | | Add test for typenames using constants shadowed later onZachary Snow2023-02-122-0/+16
* | | | Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-152-22/+51
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| * | | | Handle range offsets in packed arrays within packed structsDag Lem2023-02-052-22/+51
* | | | | Bump versiongithub-actions[bot]2023-02-151-1/+1
* | | | | Merge pull request #2995 from georgerennie/cover_precondJannis Harder2023-02-142-0/+44
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| * | | | | chformal: Note about using -coverenable with the Verific frontendJannis Harder2023-02-141-0/+5
| * | | | | chformal: Rename -coverprecond to -coverenableGeorge Rennie2022-06-182-7/+7
| * | | | | chformal: Test -coverprecond and reuse the src attributeJannis Harder2022-06-182-2/+27
| * | | | | chformal: Add -coverprecond optionGeorge Rennie2022-06-181-0/+14
* | | | | | Merge pull request #3126 from georgerennie/equiv_make_assertionsJannis Harder2023-02-142-27/+97
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| * | | | | | equiv_make: Add -make_assert optionGeorge Rennie2022-06-242-27/+97
* | | | | | | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
* | | | | | | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
* | | | | | | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
* | | | | | | Bump versiongithub-actions[bot]2023-02-141-1/+1