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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-192-3/+121
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fine tune ice40_dsp.pmg, add support for packing subsets of registersEddie Hung2019-07-194-35/+47
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ice40 signed multipliersEddie Hung2019-07-191-13/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in BEddie Hung2019-07-191-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1829-228/+405
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| * | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1828-195/+387
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ice40_dsp to accept $__MUL16X16 tooEddie Hung2019-07-181-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check if RHS is empty firstEddie Hung2019-07-181-0/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make consistentEddie Hung2019-07-181-1/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not autoremove ffP aor muxPEddie Hung2019-07-181-2/+0
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-182-12/+22
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve A/B reg packingEddie Hung2019-07-182-6/+11
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not autoremove A/B registers since they might have other consumersEddie Hung2019-07-181-2/+0
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrong wildcard symbolEddie Hung2019-07-181-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-172-5/+11
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::remove_const() to return SigSpec&Eddie Hung2019-07-172-2/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed extensionEddie Hung2019-07-162-6/+6
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si...David Shah2019-07-162-4/+8
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support {A,B,P}REG packingEddie Hung2019-07-162-55/+94
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::extract to allow negative lengthEddie Hung2019-07-161-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 18:17:39 +0000