iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	added sat -falsify	Clifford Wolf	2014-02-04	1	-4/+28
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	3	-9/+45
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*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04	2	-7/+48
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*	presentation progress	Clifford Wolf	2014-02-04	2	-11/+55
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*	presentation progress	Clifford Wolf	2014-02-03	6	-1/+152
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*	Addred sat option -ignore_unknown_cells	Clifford Wolf	2014-02-03	1	-3/+17
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	11	-78/+186
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*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03	1	-50/+10
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*	More opt_const -mux_bool features	Clifford Wolf	2014-02-02	1	-7/+46
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*	presentation progress	Clifford Wolf	2014-02-02	19	-40/+194
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*	Added opt_const -mux_bool	Clifford Wolf	2014-02-02	2	-7/+47
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*	Added support for inverter chains to opt_const	Clifford Wolf	2014-02-02	1	-1/+21
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*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02	2	-0/+10
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*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02	1	-15/+18
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*	Added constant-clock case to opt_rmdff	Clifford Wolf	2014-02-02	1	-0/+8
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*	presentation progress	Clifford Wolf	2014-02-02	10	-0/+80
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*	Added show -notitle option	Clifford Wolf	2014-02-02	1	-4/+14
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*	Added delete command	Clifford Wolf	2014-02-02	2	-0/+135
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*	Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax	Clifford Wolf	2014-02-02	1	-5/+22
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*	presentation progress	Clifford Wolf	2014-02-02	2	-10/+20
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*	presentation progress	Clifford Wolf	2014-02-02	1	-10/+158
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02	1	-7/+20
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*	Fixed a bug in miter command	Clifford Wolf	2014-02-01	1	-2/+2
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*	Added sat -show-inputs and -show-outputs	Clifford Wolf	2014-02-01	1	-1/+24
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*	Added show -color support for cells and finished show -label implementation	Clifford Wolf	2014-02-01	1	-13/+36
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*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01	2	-22/+25
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	6	-0/+48
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*	Added note about SystemVerilog assert statement to README	Clifford Wolf	2014-02-01	1	-0/+5
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*	Added miter command	Clifford Wolf	2014-02-01	2	-0/+307
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*	Progress on presentation	Clifford Wolf	2014-01-31	3	-5/+194
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31	1	-6/+11
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*	presentation progress	Clifford Wolf	2014-01-30	2	-7/+157
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*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	2	-1/+25
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*	Added yosys -H for command list	Clifford Wolf	2014-01-30	1	-1/+7
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*	presentation progress	Clifford Wolf	2014-01-29	2	-4/+36
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*	presentation progress	Clifford Wolf	2014-01-29	10	-2/+174
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*	Tiny change in example script in README	Clifford Wolf	2014-01-29	1	-1/+1
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*	Added -h command line option	Clifford Wolf	2014-01-29	1	-2/+8
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*	Added test comments to techlibs/cmos/cmos_cells.lib	Clifford Wolf	2014-01-29	1	-0/+2
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*	Updated ABC to hg rev e6b09e1	Clifford Wolf	2014-01-29	1	-1/+1
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	4	-6/+20
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*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29	1	-105/+305
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*	presentation progress	Clifford Wolf	2014-01-28	2	-4/+237
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*	Renamed manual/FILES_* directories	Clifford Wolf	2014-01-28	29	-9/+9
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*	Progress on presentation	Clifford Wolf	2014-01-28	2	-8/+69
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*	Progress on presentation	Clifford Wolf	2014-01-27	2	-5/+79
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*	Added first presentation slides	Clifford Wolf	2014-01-27	7	-1/+105
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*	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	Clifford Wolf	2014-01-26	1	-1/+5
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\| *	root bug corrected	Ahmed Irfan	2014-01-25	1	-1/+5
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* \|	Merge pull request #21 from hansiglaser/master	Clifford Wolf	2014-01-25	2	-17/+34
\|\ \ \| \| \| \| \| \|	beautified write_intersynth, enabled multiple "-map" for the extract pass