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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-02 22:41:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-02 22:41:24 +0100 |
| commit | de336d93b22feea3f36883fac9f92c3f175e91e4 (patch) | |
| tree | fdbd73fd34b5fc6bc8ab3bdf553621fa340626d9 | |
| parent | 982c9da011f51913e3388334aebc407b11647bdc (diff) | |
| download | yosys-de336d93b22feea3f36883fac9f92c3f175e91e4.tar.gz yosys-de336d93b22feea3f36883fac9f92c3f175e91e4.tar.bz2 yosys-de336d93b22feea3f36883fac9f92c3f175e91e4.zip | |
More opt_const -mux_bool features
| -rw-r--r-- | passes/opt/opt_const.cc | 53 |
1 files changed, 46 insertions, 7 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 535dd02fc..2bb542c29 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -244,20 +244,59 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && + cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]); goto next_cell; } - if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) { + if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && + cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) { cell->connections["\\A"] = cell->connections["\\S"]; cell->connections.erase("\\B"); cell->connections.erase("\\S"); - cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\A_SIGNED"] = 0; - cell->parameters.erase("\\WIDTH"); - cell->type = "$not"; + if (cell->type == "$mux") { + cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_SIGNED"] = 0; + cell->parameters.erase("\\WIDTH"); + cell->type = "$not"; + } else + cell->type = "$_INV_"; + did_something = true; + goto next_cell; + } + + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1)) { + cell->connections["\\A"] = cell->connections["\\S"]; + cell->connections.erase("\\S"); + if (cell->type == "$mux") { + cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_SIGNED"] = 0; + cell->parameters["\\B_SIGNED"] = 0; + cell->parameters.erase("\\WIDTH"); + cell->type = "$and"; + } else + cell->type = "$_AND_"; + did_something = true; + goto next_cell; + } + + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + cell->connections["\\B"] = cell->connections["\\S"]; + cell->connections.erase("\\S"); + if (cell->type == "$mux") { + cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_SIGNED"] = 0; + cell->parameters["\\B_SIGNED"] = 0; + cell->parameters.erase("\\WIDTH"); + cell->type = "$or"; + } else + cell->type = "$_or_"; did_something = true; goto next_cell; } |