| Commit message (Expand) | Author | Age | Files | Lines | ||
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| ... | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-lut <file>" support to abc9 | Eddie Hung | 2019-04-09 | 1 | -13/+31 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-box" option to abc9 | Eddie Hung | 2019-04-09 | 1 | -7/+22 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'setundef -zero' call prior to aigmap in abc9 | Eddie Hung | 2019-04-09 | 1 | -0/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Comment out | Eddie Hung | 2019-04-09 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 2 | -1/+14 | |
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 140 | -1863/+4709 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | / / | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1082 from corecode/u4k | David Shah | 2019-06-10 | 1 | -0/+24 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 | |
| | |/ / / / / / / / / / / / / / / / / / / / / / / / / / | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs | Clifford Wolf | 2019-06-08 | 1 | -12/+42 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 | |
| | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger | Clifford Wolf | 2019-06-07 | 27 | -45/+128 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Add read_aiger to CHANGELOG | Eddie Hung | 2019-06-07 | 1 | -0/+1 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 | |
| | |/ / / / / / / / / / / / / / / / / / / / / / / / / | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 4 | -50/+38 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 10 | -5/+107 | |
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| | | | * | | | | | | | | | | | | | | | | | | | | | | | | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 10 | -5/+107 | |
| | | | | |_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | / | | | | | | | | | | | | | | | | | | | | | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tux3-implicit_named_connection' | Clifford Wolf | 2019-06-07 | 4 | -3/+40 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 3 | -13/+2 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 5 | -4/+52 | |
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| | | | * | | | | | | | | | | | | | | | | | | | | | | | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 5 | -12/+59 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1076 from thasti/centos7-build-fix | Clifford Wolf | 2019-06-07 | 1 | -1/+0 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | remove boost/log/exceptions.hpp from wrapper generator | Stefan Biereigel | 2019-06-07 | 1 | -1/+0 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ... | Maciej Kurc | 2019-06-04 | 4 | -0/+46 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iob | David Shah | 2019-06-06 | 1 | -0/+15 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | ECP5: implement all Diamond I/O buffer primitives. | whitequark | 2019-06-06 | 1 | -0/+15 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 | |
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index : iCE40/yosys | |
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