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* Merge pull request #945 from YosysHQ/clifford/libwbClifford Wolf2019-04-229-39/+124
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| * Disable blackbox detection in techmap filesClifford Wolf2019-04-221-1/+1
| * Fix testsClifford Wolf2019-04-212-2/+3
| * Add "noblackbox" attributeClifford Wolf2019-04-212-18/+33
| * New behavior for front-end handling of whiteboxesClifford Wolf2019-04-206-34/+103
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* Merge pull request #943 from YosysHQ/clifford/whiteboxClifford Wolf2019-04-2027-55/+157
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| * Add "techmap -wb", use in formal flowsClifford Wolf2019-04-203-6/+13
| * Check blackbox attribute in techmap/simplemapClifford Wolf2019-04-202-2/+2
| * Add "wbflip" commandClifford Wolf2019-04-203-3/+45
| * Revert "write_json to not write contents (cells/wires) of whiteboxes"Eddie Hung2019-04-181-59/+56
| * write_json to not write contents (cells/wires) of whiteboxesEddie Hung2019-04-181-56/+59
| * Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-182-7/+21
| * Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-1823-42/+81
* | Merge pull request #942 from YosysHQ/clifford/fix931Clifford Wolf2019-04-202-5/+63
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| * | Improve proc full_case detection and handling, fixes #931Clifford Wolf2019-04-182-5/+63
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* | Improve "show" handling of 0/1/X/Z paddingClifford Wolf2019-04-201-2/+21
* | Change "ne" to "neq" in btor2 outputClifford Wolf2019-04-191-1/+1
* | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
* | Spelling fixesEddie Hung2019-04-191-2/+2
* | Update to ABC 3709744Clifford Wolf2019-04-181-1/+1
* | Merge pull request #917 from YosysHQ/eddie/fix_retimeEddie Hung2019-04-184-38/+46
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| * Fix abc's remap_name to not ignore [^0-9] when extracting sidEddie Hung2019-04-181-12/+16
| * ABC to call retime all the timeEddie Hung2019-04-181-15/+11
| * Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-1811-15/+15
| * Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-187-75/+72
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* | Update to ABC d1b6413Clifford Wolf2019-04-171-1/+1
* | Merge pull request #939 from YosysHQ/revert895Eddie Hung2019-04-161-28/+0
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| * | Revert #895Eddie Hung2019-04-161-28/+0
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* | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
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| * | Revert "Recognise default entry in case even if all cases covered (fix for #9...Eddie Hung2019-04-152-4/+3
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* | Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
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| * | README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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* | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
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| * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| * | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| * | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
* | | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
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| * | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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* | | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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| * | Add default entry to testcaseEddie Hung2019-04-111-2/+3
| * | Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
| * Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"Eddie Hung2019-04-101-2/+0
| * Revert ""&nf -D 0" fails => use "-D 1" instead"Eddie Hung2019-04-101-1/+1
| * Merge remote-tracking branch 'origin/master' into eddie/fix_retimeEddie Hung2019-04-102-4/+5
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* | Fix a few typosEddie Hung2019-04-081-3/+3
* | Merge pull request #919 from YosysHQ/multiport_transpClifford Wolf2019-04-081-1/+2
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| * | memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
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| * Add retime testEddie Hung2019-04-051-0/+6
| * Fix S0 -> S1Eddie Hung2019-04-051-1/+1