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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 02:07:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-22 02:07:36 +0200 |
| commit | 7b35d5759289f7a3139c6eaa525ef737b8d5d82b (patch) | |
| tree | 4ed5fa744185b1a985f74e03cd2a1e5e4cb48d9c | |
| parent | d38f0c1a96c036df4ef67ad2f945dd229e1c3b8e (diff) | |
| download | yosys-7b35d5759289f7a3139c6eaa525ef737b8d5d82b.tar.gz yosys-7b35d5759289f7a3139c6eaa525ef737b8d5d82b.tar.bz2 yosys-7b35d5759289f7a3139c6eaa525ef737b8d5d82b.zip | |
Disable blackbox detection in techmap files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index ee319b6e6..1a4318460 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1036,7 +1036,7 @@ struct TechmapPass : public Pass { simplemap_get_mappers(worker.simplemap_mappers); std::vector<std::string> map_files; - std::string verilog_frontend = "verilog -nooverwrite"; + std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; int max_iter = -1; size_t argidx; |