| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | | | Update README.md | Clifford Wolf | 2019-10-05 | 1 | -1/+1 | |
| * | | | | | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fix | Miodrag Milanović | 2019-10-05 | 2 | -2/+7 | |
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| | * | | | | | | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 2 | -2/+7 | |
| * | | | | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| * | | | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 2 | -5/+19 | |
| * | | | | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
| * | | | | | | | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 | |
| * | | | | | | | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again | Eddie Hung | 2019-10-04 | 1 | -0/+6 | |
| * | | | | | | | Add Const::{begin,end,empty}() | Eddie Hung | 2019-10-04 | 1 | -0/+3 | |
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| * | | | | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
| * | | | | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| * | | | | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
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| * | | | | | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 | |
| * | | | | | Update ABC to git rev 623b5e8 | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| * | | | | | Bump version | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| * | | | | | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 | |
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| | * | | | | | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 | |
| | * | | | | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 | |
| * | | | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 2 | -6/+50 | |
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| | * | | | | | | Add quick test | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
| | * | | | | | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 | |
| * | | | | | | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 2 | -27/+56 | |
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| | * | | | | | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 | |
| | * | | | | | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 2 | -21/+36 | |
| * | | | | | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 | David Shah | 2019-10-03 | 6 | -2/+184 | |
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| | * | | | | | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 | |
| | * | | | | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 | |
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| * | | | | | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire | Eddie Hung | 2019-10-02 | 2 | -0/+32 | |
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| | * | | | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 | |
| | * | | | | | | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 | |
| | * | | | | | | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
| | * | | | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
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| * | | | / / | log_dump() to support State enum | Eddie Hung | 2019-10-02 | 3 | -0/+6 | |
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| * | | | | | Merge pull request #1428 from YosysHQ/clifford/fixbtor | Clifford Wolf | 2019-10-02 | 1 | -6/+9 | |
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| | * | | | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 | |
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| * | | | | Merge pull request #1426 from YosysHQ/mmicko/fix_environ | Miodrag Milanović | 2019-10-01 | 1 | -0/+2 | |
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| | * | | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 | |
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| * / / | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 | |
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| | * | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 9 | -14/+18 | |
| | * | Check latches type one by one | Miodrag Milanovic | 2019-10-04 | 2 | -40/+25 | |
| | * | Removed top module where not needed | Miodrag Milanovic | 2019-10-04 | 4 | -37/+4 | |
| | * | Test muxes synth one by one | Miodrag Milanovic | 2019-10-04 | 2 | -38/+39 | |
| | * | Cleaned verilog code from not used defines | Miodrag Milanovic | 2019-10-04 | 1 | -6/+0 | |
| | * | Check for MULT18X18D, since that is working now | Miodrag Milanovic | 2019-10-04 | 2 | -14/+11 | |
| | * | Check flops one by one | Miodrag Milanovic | 2019-10-04 | 4 | -71/+50 | |
| | * | Removed alu and div_mod tests as agreed | Miodrag Milanovic | 2019-10-04 | 4 | -57/+0 | |
| | * | equiv_opt with -assert | Eddie Hung | 2019-09-30 | 1 | -3/+1 | |
| | * | Update resource count for alu.ys | Eddie Hung | 2019-09-30 | 1 | -3/+3 | |
| | * | Move $x to end as per 7f0eec8 | Eddie Hung | 2019-09-30 | 1 | -1/+1 | |
| | * | Update fsm.ys resource count | Eddie Hung | 2019-09-30 | 1 | -3/+3 | |
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index : iCE40/yosys | |
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