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| * | | | | | | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2019-04-01120-600/+5502
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| * \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-03-0412-28/+124
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| * \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-03-0131-105/+622
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| * \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-02-2539-222/+2479
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-02-153-44/+47
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-02-11109-413/+3479
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| * | | | | | | | | | | | | | | Fix botched merge in CHANGELOGJim Lawson2018-12-181-1/+0
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2018-12-18128-636/+8336
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # Conflicts: # CHANGELOG # frontends/verific/verific.cc # frontends/verilog/verilog_parser.y
| * | | | | | | | | | | | | | | | Improve Verific importer blackbox handlingClifford Wolf2018-10-081-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Add "write_edif -attrprop"Clifford Wolf2018-10-081-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Fix compiler warning in verific.ccClifford Wolf2018-10-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Fix misspelling in issue_template.mdTim Ansell2018-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's been bugging me :-P
| * | | | | | | | | | | | | | | | Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-081-1/+1
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| * | | | | | | | | | | | | | | | Add inout ports to cells_xtra.vClifford Wolf2018-10-082-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-081-0/+1
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| * | | | | | | | | | | | | | | | Fix for issue 594.Tom Verbeure2018-10-081-1/+2
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| * | | | | | | | | | | | | | | | Add read_verilog $changed supportDan Gisselquist2018-10-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | ecp5: Don't map ROMs to DRAMDavid Shah2018-10-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | | | | | | | | | | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Update to v2 YosysVS templateClifford Wolf2018-10-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-10-083-6/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-10-081-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Update CHANGELOGClifford Wolf2018-10-081-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-10-081-11/+11
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| * | | | | | | | | | | | | | | | Update CHANGLELOGClifford Wolf2018-10-081-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Update ChangelogClifford Wolf2018-10-081-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | Fix Cygwin build and document needed packagesMiodrag Milanovic2018-10-083-1/+14
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| * | | | | | | | | | | | | | | | Fixed typo in "verilog_write" help messageacw12512018-10-082-5/+5
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| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2018-09-1711-14/+78
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge pull request #4 from YosysHQ/masterJim Lawson2018-08-283-23/+112
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge with YosysHQ master
* | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_bracesEddie Hung2019-05-211-5/+9
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| * | | | | | | | | | | | | | | | | | Rename labelEddie Hung2019-05-211-6/+5
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| * | | | | | | | | | | | | | | | | | Try againEddie Hung2019-05-211-4/+10
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| * | | | | | | | | | | | | | | | | | Fix warningEddie Hung2019-05-211-3/+2
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* | | | | | | | | | | | | | | | | | Merge pull request #1017 from Kmanfi/bigger_verilog_filesClifford Wolf2019-05-181-1/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read bigger Verilog files.
| * | | | | | | | | | | | | | | | | | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
|/ / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
* | | | | | | | | | | | | | | | | | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-163-2/+24
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| * | | | | | | | | | | | | | | | | | Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | | | | | | | | | | | | | | | | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | | | | | | | | | | | | | | | | | Merge pull request #1012 from YosysHQ/clifford/sigspecrwClifford Wolf2019-05-153-17/+92
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Another rounds of opt_clean improvements
| * | | | | | | | | | | | | | | | | | | Improvements in opt_cleanClifford Wolf2019-05-151-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-152-7/+82
|/ / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | Do not leak file descriptors in cover.ccClifford Wolf2019-05-151-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | Merge pull request #1011 from hzeller/fix-constructing-string-from-intClifford Wolf2019-05-152-2/+3
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two instances of integer-assignment to string.
| * | | | | | | | | | | | | | | | | | | Fix two instances of integer-assignment to string.Henner Zeller2019-05-142-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o In cover.cc, the int-result of mkstemps() was assigned to a string and silently interpreted as a single-character filename with a funny value. Fix with the intent: assign the filename. o in libparse.cc, an int was assigned to a string, but depending on visible constructors, this is ambiguous. Explicitly cast this to a char.
* | | | | | | | | | | | | | | | | | | | Merge pull request #1010 from hzeller/yacc-self-containedClifford Wolf2019-05-152-2/+18
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the generated *.tab.hh include all the headers needed
| * | | | | | | | | | | | | | | | | | | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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* | | | | | | | | | | | | | | | | | | | Merge pull request #1008 from thasti/fix_libyosys_buildClifford Wolf2019-05-151-5/+6
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | Create $(LIBDIR) to fix broken build in isolated environments
| * | | | | | | | | | | | | | | | | | | extract python prefix to allow overridingStefan Biereigel2019-05-141-1/+2
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| * | | | | | | | | | | | | | | | | | | remove ldconfig callStefan Biereigel2019-05-141-1/+0
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generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 15:58:10 +0000