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* Add test exampleMiodrag Milanovic2023-02-274-0/+51
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* Handle more wide case selector typesMiodrag Milanovic2023-02-271-14/+42
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* Bump versiongithub-actions[bot]2023-02-241-1/+1
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* Merge pull request #3685 from YosysHQ/update-abcCatherine2023-02-231-1/+1
|\ | | | | Update abc
| * Update abc.Catherine2023-02-231-1/+1
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* Bump versiongithub-actions[bot]2023-02-211-1/+1
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* Merge pull request #3403 from KrystalDelusion/mem-testsN. Engelhardt2023-02-2026-14/+1696
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| * Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
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| * bug3205.ys removedKrystalDelusion2023-02-211-57/+0
| | | | | | | | Made redundant by TDP test(s) in memories.ys
| * Removing extra `default_nettype` linesKrystalDelusion2023-02-211-2/+0
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| * Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
| | | | | | | | Explicitly declare -top in synth_intel_alm.
| * More tests in memlib/generate.pyKrystalDelusion2023-02-2113-12/+1180
| | | | | | | | Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
| * Tests for ram_style = "huge"KrystalDelusion2023-02-214-0/+219
| | | | | | | | iCE40 SPRAM and Xilinx URAM
| * Testing TDP synth mappingKrystalDelusion2023-02-213-0/+49
| | | | | | | | | | New common sync_ram_tdp. Used in ecp5 and gatemate mem*.ys.
| * Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
| | | | | | | | Uses verilog code from User Guide 901 (2021.1)
| * Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
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* Bump versiongithub-actions[bot]2023-02-181-1/+1
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* Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dregN. Engelhardt2023-02-171-1/+1
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| * Check DREG attributeOliver Keszöcze2023-02-171-1/+1
|/ | | The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
* Bump versiongithub-actions[bot]2023-02-171-1/+1
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* fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Bump versiongithub-actions[bot]2023-02-161-1/+1
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* Merge pull request #3672 from jix/yw-cosim-hierarchy-fixesJannis Harder2023-02-151-1/+25
|\ | | | | sim: For yw cosim, drive parent module's signals for input ports
| * sim: For yw cosim, drive parent module's signals for input portsJannis Harder2023-02-131-1/+25
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* | Merge pull request #3675 from daglem/struct-item-queriesJannis Harder2023-02-152-12/+161
|\ \ | | | | | | Support for data and array queries on struct/union item expressions
| * | Corrected tests for data and array queries on struct/union item expressionsDag Lem2023-02-151-80/+85
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| * | Support for data and array queries on struct/union item expressionsDag Lem2023-02-152-12/+156
| | | | | | | | | | | | For now, $bits, $left, $right, $low, $high, and $size are supported.
* | | Merge pull request #3671 from zachjs/masterJannis Harder2023-02-152-0/+16
|\ \ \ | |/ / |/| | Add test for typenames using constants shadowed later on
| * | Add test for typenames using constants shadowed later onZachary Snow2023-02-122-0/+16
| | | | | | | | | | | | | | | This possible edge case came up while reviewing #3555. It is currently handled correctly, but there is no clear test coverage.
* | | Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-152-22/+51
|\ \ \ | | | | | | | | Handle range offsets in packed arrays within packed structs
| * | | Handle range offsets in packed arrays within packed structsDag Lem2023-02-052-22/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
* | | | Bump versiongithub-actions[bot]2023-02-151-1/+1
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* | | | Merge pull request #2995 from georgerennie/cover_precondJannis Harder2023-02-142-0/+44
|\ \ \ \ | | | | | | | | | | chformal: Add -coverenable option
| * | | | chformal: Note about using -coverenable with the Verific frontendJannis Harder2023-02-141-0/+5
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| * | | | chformal: Rename -coverprecond to -coverenableGeorge Rennie2022-06-182-7/+7
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| * | | | chformal: Test -coverprecond and reuse the src attributeJannis Harder2022-06-182-2/+27
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| * | | | chformal: Add -coverprecond optionGeorge Rennie2022-06-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | This inserts $cover cells to cover the enable signal (precondition) for the selected formal cells.
* | | | | Merge pull request #3126 from georgerennie/equiv_make_assertionsJannis Harder2023-02-142-27/+97
|\ \ \ \ \ | | | | | | | | | | | | equiv_make: Add -make_assert option
| * | | | | equiv_make: Add -make_assert optionGeorge Rennie2022-06-242-27/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a -make_assert flag to equiv_make. When used, the pass generates $eqx and $assert cells to encode equivalence instead of $equiv.
* | | | | | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
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* | | | | | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
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* | | | | | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
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* | | | | | Bump versiongithub-actions[bot]2023-02-141-1/+1
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* | | | | | Merge pull request #3669 from jix/fix-xprop-tests-yosys-callJannis Harder2023-02-133-52/+60
|\ \ \ \ \ \ | | | | | | | | | | | | | | tests: Fix path of yosys invocation in xprop tests
| * | | | | | xprop tests: Make iverilog invocation more portableJannis Harder2023-02-131-3/+3
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| * | | | | | xprop: Test fixes and abort on test failureJannis Harder2023-02-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass.
| * | | | | | xprop: Smaller subset of tests to run by defaultJannis Harder2023-02-131-44/+53
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| * | | | | | verilog_backend: Do not run bwmuxmap even if in expr modeJannis Harder2023-02-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While bwmuxmap generates equivalent logic, it doesn't propagate x bits in the same way, which can be relevant when writing verilog.
| * | | | | | tests: Fix path of yosys invocation in xprop testsJannis Harder2023-02-101-1/+1
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | For now xprop test failures are still expected and ignored, but without this change, they did not even run unless the yosys build was in path.
* | | | | | Bump versiongithub-actions[bot]2023-02-131-1/+1
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