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* Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
* Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
* ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
* Merge pull request #1457 from xobs/python-binary-nameMiodrag Milanović2019-10-196-9/+9
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| * Makefile: don't assume python is called `python3`Sean Cross2019-10-196-9/+9
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* Merge pull request #1454 from YosysHQ/mmicko/common_testsMiodrag Milanović2019-10-18166-1763/+455
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| * fixed errorMiodrag Milanovic2019-10-181-1/+1
| * Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
| * Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
| * Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
| * Share common testsMiodrag Milanovic2019-10-18103-1316/+178
| * fix yosys pathMiodrag Milanovic2019-10-181-2/+2
| * Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
| * Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18151-5/+5
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* Add async2syncMiodrag Milanovic2019-10-182-8/+8
* Merge pull request #1435 from YosysHQ/mmicko/efinixMiodrag Milanović2019-10-1827-1/+572
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| * Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-18156-896/+3156
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* | Merge pull request #1434 from YosysHQ/mmicko/anlogicMiodrag Milanović2019-10-1821-0/+430
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| * \ Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-18136-896/+2726
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* | | Merge pull request #1421 from YosysHQ/eddie/pr1352Miodrag Milanović2019-10-1833-0/+669
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| * \ \ Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-18119-987/+2470
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* | | | Merge pull request #1420 from YosysHQ/eddie/pr1363Miodrag Milanović2019-10-1829-47/+544
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| * | | | hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| * | | | Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| * | | | remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| * | | | remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| * | | | split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| * | | | Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| * | | | Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| * | | | Fix formattingMiodrag Milanovic2019-10-171-1/+8
| * | | | Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
| * | | | Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
| * | | | Test per flip-flop typeMiodrag Milanovic2019-10-172-47/+37
| * | | | Add -assertEddie Hung2019-10-171-1/+1
| * | | | Use built-in async2sync call as per #1417Eddie Hung2019-10-171-4/+0
| * | | | Update mul test to DSP48E1Eddie Hung2019-10-171-9/+2
| * | | | Update area for div_modEddie Hung2019-10-171-6/+6
| * | | | Add comment for lack of tristate logic pointing to #1225Eddie Hung2019-10-171-1/+1
| * | | | Move $x to end as 7f0eec8Eddie Hung2019-10-171-1/+1
| * | | | adffs test update (equiv_opt -multiclock)SergeyDegtyar2019-10-171-5/+6
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Fix div_mod testSergey2019-10-171-1/+1
| * | | | Add comment with expected behavior for latches,tribuf tests;Update adffs testSergeyDegtyar2019-10-174-14/+11
| * | | | Fix latches.ys testSergeyDegtyar2019-10-171-4/+3
| * | | | Remove xilinx_ug901 tests (will be moved to yosys-tests)SergeyDegtyar2019-10-1789-2963/+0
| * | | | Add smoke tests to tests/xilinxSergeyDegtyar2019-10-1730-9/+655
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