| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | Some test related fixes | Clifford Wolf | 2015-02-12 | 6 | -156/+6 | |
| * | | Added "proc_dlatch" | Clifford Wolf | 2015-02-12 | 3 | -1/+311 | |
| * | | Less aggressive "share" defaults | Clifford Wolf | 2015-02-10 | 1 | -4/+6 | |
| * | | Improved read_verilog support for empty behavioral statements | Clifford Wolf | 2015-02-10 | 1 | -6/+2 | |
| * | | Added "scc -expect <N> -nofeedback" | Clifford Wolf | 2015-02-10 | 1 | -7/+48 | |
| * | | Some hashlib improvements | Clifford Wolf | 2015-02-09 | 1 | -9/+37 | |
| * | | Various changes to release checklist | Clifford Wolf | 2015-02-09 | 2 | -45/+28 | |
| * | | Fixed creation of command reference in manual | Clifford Wolf | 2015-02-09 | 3 | -9/+16 | |
| * | | We are now in 0.5+ development | Clifford Wolf | 2015-02-09 | 1 | -1/+1 | |
| * | | Yosys 0.5 | Clifford Wolf | 2015-02-09 | 1 | -1/+1 | |
| * | | Bugfix in "make vcxsrc" | Clifford Wolf | 2015-02-09 | 1 | -1/+1 | |
| * | | Updated command reference in manual | Clifford Wolf | 2015-02-09 | 1 | -75/+440 | |
| * | | Various presentation fixes | Clifford Wolf | 2015-02-09 | 2 | -8/+15 | |
| * | | Fixed iterator invalidation bug in "rename" command | Clifford Wolf | 2015-02-09 | 1 | -3/+4 | |
| * | | CodingReadme update | Clifford Wolf | 2015-02-08 | 1 | -0/+1 | |
| * | | Fixed bug in "show -format .." | Clifford Wolf | 2015-02-08 | 1 | -1/+1 | |
| * | | Added new APIs to changelog | Clifford Wolf | 2015-02-08 | 1 | -0/+1 | |
| * | | Fixed eval_select_op() api | Clifford Wolf | 2015-02-08 | 2 | -2/+2 | |
| * | | Added eval_select_args() and eval_select_op() | Clifford Wolf | 2015-02-08 | 2 | -4/+29 | |
| * | | Minor "make vgtest" changes | Clifford Wolf | 2015-02-08 | 2 | -2/+6 | |
| * | | Various ModIndex improvements | Clifford Wolf | 2015-02-08 | 1 | -13/+54 | |
| * | | Added Yosys 0.5 Changelog | Clifford Wolf | 2015-02-08 | 1 | -4/+46 | |
| * | | Various updates to CodingReadme | Clifford Wolf | 2015-02-08 | 1 | -10/+13 | |
| * | | Added equiv_add | Clifford Wolf | 2015-02-08 | 2 | -0/+90 | |
| * | | Ignore explicit assignments to constants in HDL code | Clifford Wolf | 2015-02-08 | 1 | -0/+14 | |
| * | | Fixed a bug with autowire bit size | Clifford Wolf | 2015-02-08 | 1 | -9/+3 | |
| * | | fixed typo | Clifford Wolf | 2015-02-08 | 1 | -1/+1 | |
| * | | Added "yosys-config --build modname.so cppsources.." | Clifford Wolf | 2015-02-08 | 1 | -2/+12 | |
| * | | Added SigSpec::has_const() | Clifford Wolf | 2015-02-08 | 2 | -0/+13 | |
| * | | Cleanup in add_share_file make macro | Clifford Wolf | 2015-02-08 | 1 | -3/+3 | |
| * | | Removed "make mklibyosys" | Clifford Wolf | 2015-02-07 | 1 | -14/+0 | |
| * | | Improved building of plugins | Clifford Wolf | 2015-02-07 | 2 | -3/+36 | |
| * | | Added "make uninstall" | Clifford Wolf | 2015-02-07 | 1 | -0/+4 | |
| * | | Added cell->known(), cell->input(portname), cell->output(portname) | Clifford Wolf | 2015-02-07 | 2 | -0/+39 | |
| * | | Added "select -read" | Clifford Wolf | 2015-02-06 | 1 | -5/+39 | |
| * | | Auto-detect TCL version | Clifford Wolf | 2015-02-05 | 2 | -2/+2 | |
| * | | Added onehot attribute | Clifford Wolf | 2015-02-04 | 3 | -0/+19 | |
| * | | Fixed opt_clean performance bug | Clifford Wolf | 2015-02-04 | 1 | -26/+26 | |
| * | | Disabled (unused) Xilinx tristate buffers | Clifford Wolf | 2015-02-04 | 1 | -6/+6 | |
| * | | Using design->selected_modules() in opt_* | Clifford Wolf | 2015-02-03 | 5 | -36/+20 | |
| * | | Skip blackbox modules in design->selected_modules() | Clifford Wolf | 2015-02-03 | 1 | -3/+5 | |
| * | | Added "yosys -L logfile" | Clifford Wolf | 2015-02-03 | 1 | -1/+7 | |
| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2015-02-01 | 2 | -3/+3 | |
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| | * \ | Merge pull request #48 from rubund/master | Clifford Wolf | 2015-02-01 | 2 | -3/+3 | |
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| | | * | | Fixed typos found by lintian | Ruben Undheim | 2015-02-01 | 2 | -3/+3 | |
| * | | | | no support for 6-series xilinx devices | Clifford Wolf | 2015-02-01 | 1 | -1/+1 | |
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| * / / | Improved performance in equiv_simple | Clifford Wolf | 2015-02-01 | 2 | -23/+73 | |
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| * | | Removed old XST-based xilinx examples | Clifford Wolf | 2015-02-01 | 11 | -208/+0 | |
| * | | Added Xilinx example for Basys3 board | Clifford Wolf | 2015-02-01 | 9 | -1/+84 | |
| * | | Added EDIF backend support for multi-bit cell ports | Clifford Wolf | 2015-02-01 | 1 | -11/+10 | |
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index : iCE40/yosys | |
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