| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | Space | Eddie Hung | 2019-07-01 | 1 | -0/+1 | |
| | * | | | Move CHANGELOG entry from yosys-0.8 to 0.9 | Eddie Hung | 2019-07-01 | 1 | -7/+1 | |
| | * | | | Merge branch 'master' into eddie/script_from_wire | Eddie Hung | 2019-07-01 | 4 | -5/+15 | |
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| | * | | | Merge branch 'master' into eddie/script_from_wire | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
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| | * | | | | Try command in another module | Eddie Hung | 2019-06-28 | 1 | -0/+3 | |
| | * | | | | Add to CHANGELOG | Eddie Hung | 2019-06-28 | 1 | -0/+6 | |
| | * | | | | Support ability for "script -select" to take commands from wires | Eddie Hung | 2019-06-28 | 1 | -8/+39 | |
| | * | | | | Add test | Eddie Hung | 2019-06-28 | 1 | -0/+17 | |
| * | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-02 | 3 | -3/+25 | |
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| | * | | | | | memory_dff: Fix checking of feedback mux input when more than one mux | David Shah | 2019-07-02 | 3 | -3/+25 | |
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| * | | / / | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi... | Clifford Wolf | 2019-07-02 | 1 | -0/+2 | |
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| * | | | | Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG | Eddie Hung | 2019-07-01 | 1 | -5/+11 | |
| * | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-07-01 | 3 | -0/+4 | |
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| | * | | | install *_nowide.lut files | Eddie Hung | 2019-06-29 | 2 | -0/+3 | |
| | * | | | Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup | Eddie Hung | 2019-06-28 | 1 | -0/+1 | |
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| | | * | | Make abc9 pass aware of optional ABCEXTERNAL override | Gabriel L. Somlo | 2019-06-28 | 1 | -0/+1 | |
| * | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
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| * | | | Replace log_assert() with meaningful log_error() | Eddie Hung | 2019-06-28 | 1 | -1/+5 | |
| * | | | Remove peepopt call in synth_xilinx since already in synth -run coarse | Eddie Hung | 2019-06-28 | 1 | -5/+0 | |
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| * | | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 | |
| * | | Fix spacing | Eddie Hung | 2019-06-28 | 1 | -2/+2 | |
| * | | Merge pull request #1098 from YosysHQ/xaig | Eddie Hung | 2019-06-28 | 45 | -247/+3642 | |
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| | * | | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 | |
| | * | | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 | |
| | * | | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 | |
| | * | | Update synth_ice40 -device doc to be relevant for -abc9 only | Eddie Hung | 2019-06-28 | 1 | -2/+2 | |
| | * | | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | * | | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | * | | Fix DO4 typo | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | * | | Reduce diff with upstream | Eddie Hung | 2019-06-27 | 1 | -4/+2 | |
| | * | | Extraneous newline | Eddie Hung | 2019-06-27 | 1 | -1/+0 | |
| | * | | Remove noise from ice40/cells_sim.v | Eddie Hung | 2019-06-27 | 1 | -5/+0 | |
| | * | | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 5 | -82/+84 | |
| | * | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 | |
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| | | * \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 | |
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| | * | | | | Do not use Module::remove() iterator version | Eddie Hung | 2019-06-27 | 1 | -5/+6 | |
| | * | | | | Remove redundant doc | Eddie Hung | 2019-06-27 | 1 | -3/+0 | |
| | * | | | | Remove &retime when abc9 -fast | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
| | * | | | | Cleanup abc9.cc | Eddie Hung | 2019-06-27 | 1 | -15/+17 | |
| | * | | | | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 | |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 4 | -9/+39 | |
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| | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 0 | -0/+0 | |
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| | * | | | | | Add warning if synth_xilinx -abc9 with family != xc7 | Eddie Hung | 2019-06-27 | 1 | -0/+2 | |
| | * | | | | | Remove unneeded include | Eddie Hung | 2019-06-27 | 1 | -3/+0 | |
| | * | | | | | Merge origin/master | Eddie Hung | 2019-06-27 | 10 | -65/+480 | |
| | * | | | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -38/+38 | |
| | * | | | | | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 | |
| | * | | | | | Add WE to ECP5 dist RAM's abc_scc_break too | Eddie Hung | 2019-06-26 | 1 | -1/+1 | |
| | * | | | | | Update comment on boxes | Eddie Hung | 2019-06-26 | 2 | -4/+6 | |
| | * | | | | | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 | |
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index : iCE40/yosys | |
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