| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Output "h" extension only if boxes | Eddie Hung | 2019-08-21 | 1 | -28/+32 |
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| * | Revert "Fix omode which inserts an output if none exists (otherwise abc9 ↵ | Eddie Hung | 2019-08-21 | 1 | -8/+7 |
| | | | | | | | breaks)" This reverts commit 8182cb9d91555d5be52abbfeeb5d22af05342d8a. | ||||
| * | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 |
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| * | Fix omode which inserts an output if none exists (otherwise abc9 breaks) | Eddie Hung | 2019-08-20 | 1 | -7/+8 |
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| * | Revert "Only xaig if GetSize(output_bits) > 0" | Eddie Hung | 2019-08-20 | 1 | -149/+147 |
| | | | | | This reverts commit 7b646101e936cacd20938c20ddfbaa63ee268fb2. | ||||
| * | Only xaig if GetSize(output_bits) > 0 | Eddie Hung | 2019-08-20 | 1 | -147/+149 |
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| * | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | Merge branch 'eddie/fix_techmap' into xaig_arrival | Eddie Hung | 2019-08-20 | 4 | -1/+16 |
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| | * | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| | * | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 |
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| | * | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 |
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| * | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 |
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| * | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 |
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| * | | ecp5: remove DPR16X4 from abc_unmap.v | Eddie Hung | 2019-08-20 | 1 | -20/+0 |
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| * | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 3 | -4/+3 |
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| * | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 7 | -14/+89 |
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| * | | Add (* abc_arrival=<int> *) doc | Eddie Hung | 2019-08-20 | 1 | -0/+5 |
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| * | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 |
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| * | | Remove sequential extension | Eddie Hung | 2019-08-20 | 9 | -730/+68 |
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| * | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 |
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| * | | retime_mode -> dff_mode | Eddie Hung | 2019-08-20 | 1 | -7/+7 |
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| * | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
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| * | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
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| * | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
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| * | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 5 | -16/+23 |
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| | * | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 |
| | |\ | | | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 |
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| | | * | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 |
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| | | * | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 |
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| | | * | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| | | * | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 |
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| | | * | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
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| * | | | | Do not sigmap! | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | | | | Deprecate `abc_scc_break` attribute | Eddie Hung | 2019-08-20 | 1 | -8/+0 |
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| * | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 |
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| * | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 |
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| * | | | | Minor refactor | Eddie Hung | 2019-08-20 | 1 | -7/+6 |
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| * | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 |
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| * | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXME | Eddie Hung | 2019-08-20 | 1 | -65/+13 |
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| * | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
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| * | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 8 | -141/+334 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 24 | -112/+857 |
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| | * | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 |
| | |\ \ \ | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | ||||
| | | * | | | Clarify with 'only' | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| | | * | | | Update doc | Eddie Hung | 2019-08-19 | 1 | -3/+4 |
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| | | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 4 | -12/+12 |
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| | * | | | | Merge pull request #1298 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-20 | 12 | -93/+790 |
| | |\ \ \ \ | | | | | | | | | | | | | Improvements in pmgen | ||||
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index : iCE40/yosys | |
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