| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | Merge pull request #822 from litghost/expand_setundef | Clifford Wolf | 2019-02-21 | 1 | -0/+29 | |
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| | | * | | | | | | | | | | | Add -params mode to force undef parameters in selected cells. | Keith Rothman | 2019-02-21 | 1 | -0/+29 | |
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| | * | | | | | | | | | | | Merge pull request #818 from YosysHQ/clifford/dffsrfix | Clifford Wolf | 2019-02-21 | 1 | -6/+7 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ | Merge pull request #786 from YosysHQ/pmgen | Clifford Wolf | 2019-02-21 | 14 | -59/+1851 | |
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| | | * | | | | | | | | | | | | Fix typo in passes/pmgen/README.md | Clifford Wolf | 2019-02-21 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | | Bugfix in ice40_dsp | Clifford Wolf | 2019-02-21 | 3 | -22/+35 | |
| | | * | | | | | | | | | | | | Add ice40 test_dsp_map test case generator | Clifford Wolf | 2019-02-20 | 2 | -0/+99 | |
| | | * | | | | | | | | | | | | Add "synth_ice40 -dsp" | Clifford Wolf | 2019-02-20 | 2 | -7/+31 | |
| | | * | | | | | | | | | | | | Add FF support to wreduce | Clifford Wolf | 2019-02-20 | 2 | -1/+73 | |
| | | * | | | | | | | | | | | | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 5 | -121/+179 | |
| | | * | | | | | | | | | | | | Detect and reject cases that do not map well to iCE40 DSPs (yet) | Clifford Wolf | 2019-02-20 | 2 | -2/+17 | |
| | | * | | | | | | | | | | | | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 4 | -53/+467 | |
| | | * | | | | | | | | | | | | Add actual DSP inference to ice40_dsp pass | Clifford Wolf | 2019-02-17 | 3 | -24/+214 | |
| | | * | | | | | | | | | | | | Merge branch 'master' of github.com:YosysHQ/yosys into pmgen | Clifford Wolf | 2019-02-17 | 28 | -199/+627 | |
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| | | * | | | | | | | | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 1 | -3/+11 | |
| | | * | | | | | | | | | | | | Progress in pmgen, add pmgen README | Clifford Wolf | 2019-01-15 | 3 | -14/+260 | |
| | | * | | | | | | | | | | | | Fix pmgen "reject" statement | Clifford Wolf | 2019-01-15 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 3 | -36/+139 | |
| | | * | | | | | | | | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 3 | -21/+157 | |
| | | * | | | | | | | | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 5 | -8/+347 | |
| | | * | | | | | | | | | | | | Add mockup .pmg (pattern matcher generator) file | Clifford Wolf | 2019-01-15 | 1 | -0/+75 | |
| | * | | | | | | | | | | | | | Merge pull request #821 from eddiehung/dff_init | Clifford Wolf | 2019-02-21 | 1 | -4/+2 | |
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| | | * | | | | | | | | | | | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| * | | | | | | | | | | | | | | tests/simple to also do LUT synth | Eddie Hung | 2019-02-21 | 1 | -0/+1 | |
| * | | | | | | | | | | | | | | Working simple_abc9 tests | Eddie Hung | 2019-02-21 | 1 | -2/+2 | |
| * | | | | | | | | | | | | | | abc9 to only disconnect output ports of AND and NOT gates | Eddie Hung | 2019-02-21 | 1 | -2/+4 | |
| * | | | | | | | | | | | | | | write_xaiger to use original bit for co, not sigmap()-ed bit | Eddie Hung | 2019-02-21 | 1 | -3/+6 | |
| * | | | | | | | | | | | | | | Add abc9.v testcase to simple_abc9 | Eddie Hung | 2019-02-21 | 1 | -4/+46 | |
| * | | | | | | | | | | | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-21 | 2 | -27/+7 | |
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| | * | | | | | | | | | | | | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 | Clifford Wolf | 2019-02-21 | 1 | -6/+7 | |
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| | * | | | | / / / / / / / | Merge pull request #817 from eddiehung/dff_init | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
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| | | * | | | | | | | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
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| * | | | | | | | | | | | ABC -> ABC9 | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
| * | | | | | | | | | | | abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ | Eddie Hung | 2019-02-20 | 1 | -21/+29 | |
| * | | | | | | | | | | | read_aiger to not do -purge for clean | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
| * | | | | | | | | | | | lut/not/and suffix to be ${lut,not,and} | Eddie Hung | 2019-02-20 | 2 | -17/+17 | |
| * | | | | | | | | | | | simple_abc9 tests to now preserve memories | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
| * | | | | | | | | | | | read_aiger to also rename 0 index lut when wideports | Eddie Hung | 2019-02-20 | 1 | -2/+14 | |
| * | | | | | | | | | | | Remove swap file | Eddie Hung | 2019-02-20 | 1 | -0/+0 | |
| * | | | | | | | | | | | write_aiger: fix CI/CO and symbols | Eddie Hung | 2019-02-20 | 2 | -7/+13 | |
| * | | | | | | | | | | | Move tests/techmap/abc9 to simple_abc9 | Eddie Hung | 2019-02-20 | 4 | -23/+0 | |
| * | | | | | | | | | | | Add tests/simple_abc9 | Eddie Hung | 2019-02-20 | 1 | -0/+23 | |
| * | | | | | | | | | | | abc9 to cope with multiple modules | Eddie Hung | 2019-02-20 | 1 | -7/+11 | |
| * | | | | | | | | | | | abc9 to use & syntax for -fast, and name fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 | |
| * | | | | | | | | | | | read_aiger: new naming fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 | |
| * | | | | | | | | | | | read_aiger to name wires with internal name, less likely to clash | Eddie Hung | 2019-02-20 | 1 | -18/+15 | |
| * | | | | | | | | | | | write_xaiger to not write latches, CO/PO fixes | Eddie Hung | 2019-02-20 | 1 | -17/+26 | |
| * | | | | | | | | | | | synth to take -abc9 argument | Eddie Hung | 2019-02-20 | 1 | -5/+13 | |
| * | | | | | | | | | | | abc9 to cope with indexed wires when creating $lut from $_NOT_ | Eddie Hung | 2019-02-19 | 1 | -1/+6 | |
| * | | | | | | | | | | | Add a quick abc9 test | Eddie Hung | 2019-02-19 | 4 | -0/+29 | |
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index : iCE40/yosys | |
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