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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 17:36:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 17:36:57 -0800 |
| commit | 7f26043caf6f9810d8541caaa57151ec8fb539a1 (patch) | |
| tree | df2d05286664cd7677cfd8fa86d35aac46757b7a | |
| parent | e5b8bb9faa466adac10e81799e338aa53210adbc (diff) | |
| download | yosys-7f26043caf6f9810d8541caaa57151ec8fb539a1.tar.gz yosys-7f26043caf6f9810d8541caaa57151ec8fb539a1.tar.bz2 yosys-7f26043caf6f9810d8541caaa57151ec8fb539a1.zip | |
ABC -> ABC9
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3f0072d24..4b045cbea 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -532,7 +532,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri ifs.close(); - log_header(design, "Re-integrating ABC results.\n"); + log_header(design, "Re-integrating ABC9 results.\n"); RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); |