| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 | |
| * | | | | | | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 | |
| * | | | | | | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| * | | | | | | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 | |
| * | | | | | | | Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| | * | | | | | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 2 | -3/+12 | |
| * | | | | | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
| * | | | | | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 | |
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| * | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 | |
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| | * | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| | * | | | | | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 | |
| | * | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
| * | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 | |
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| | * | | | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 | |
| | * | | | | | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 | |
| | * | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| | * | | | | | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 | |
| | * | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
| * | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 | |
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| | * | | | | | | | Clarify with 'only' | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
| | * | | | | | | | Update doc | Eddie Hung | 2019-08-19 | 1 | -3/+4 | |
| | * | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 4 | -12/+12 | |
| | * | | | | | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 | |
| | * | | | | | | | Add doc for abc_* attributes | Eddie Hung | 2019-08-16 | 1 | -0/+16 | |
| | * | | | | | | | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 2 | -11/+21 | |
| | * | | | | | | | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 2 | -85/+80 | |
| | * | | | | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 | |
| * | | | | | | | | Merge pull request #1298 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-20 | 12 | -93/+790 | |
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| | * \ \ \ \ \ \ \ | Merge branch 'master' into clifford/pmgen | Clifford Wolf | 2019-08-20 | 13 | -39/+85 | |
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| * | | | | | | | | | Add test case for real parameters | Clifford Wolf | 2019-08-20 | 1 | -1/+10 | |
| * | | | | | | | | | Merge pull request #1308 from jakobwenzel/real_params | Clifford Wolf | 2019-08-20 | 1 | -1/+4 | |
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| | * | | | | | | | | | handle real values when deriving ast modules | Jakob Wenzel | 2019-08-19 | 1 | -1/+4 | |
| * | | | | | | | | | | Merge pull request #1309 from whitequark/proc_clean-fix-1268 | whitequark | 2019-08-20 | 6 | -2/+37 | |
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| | * | | | | | | | | | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 6 | -2/+37 | |
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| * | | | | | | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
| * | | | | | | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
| * | | | | | | | | | ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc | Eddie Hung | 2019-08-19 | 1 | -30/+30 | |
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| * | | | | | | | | Merge pull request #1306 from mmicko/gitignore_fix | Clifford Wolf | 2019-08-19 | 1 | -2/+1 | |
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| | * | | | | | | | | Ignore all generated headers for pmgen pass | Miodrag Milanovic | 2019-08-18 | 1 | -2/+1 | |
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| * | | | | | | | | Add *.sv to tests/simple_abc9/.gitignore | Clifford Wolf | 2019-08-19 | 1 | -0/+1 | |
| | | * | | | | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen | Clifford Wolf | 2019-08-19 | 110 | -2078/+3173 | |
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| * | | | | | | | | Merge pull request #1305 from YosysHQ/clifford/testfast | Clifford Wolf | 2019-08-19 | 8 | -38/+48 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into clifford/testfast | Eddie Hung | 2019-08-18 | 91 | -1110/+2215 | |
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| * | | | | | | | | Merge pull request #1290 from YosysHQ/eddie/pr1266_again | whitequark | 2019-08-18 | 20 | -180/+180 | |
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| | * \ \ \ \ \ \ \ | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 90 | -3441/+4565 | |
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| * | | | | | | | | | Merge pull request #1283 from YosysHQ/clifford/fix1255 | Clifford Wolf | 2019-08-17 | 6 | -17/+15 | |
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