| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 12 | -227/+600 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Merge pull request #841 from mmicko/master | Clifford Wolf | 2019-03-01 | 1 | -2/+3 |
| |\ | | | | | Fix ECP5 cells_sim for iverilog | ||||
| | * | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 |
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| * | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode | Clifford Wolf | 2019-02-28 | 1 | -2/+2 |
| |\ | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | ||||
| | * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 |
| | | | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net> | ||||
| * | | Hotfix for "make test" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #837 from YosysHQ/clifford/fix835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 |
| |\ \ | | | | | | | Fix multiple issues in wreduce FF handling, fixes #835 | ||||
| | * | | Fix multiple issues in wreduce FF handling, fixes #835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #834 from YosysHQ/clifford/siminit | Clifford Wolf | 2019-02-28 | 2 | -3/+12 |
| |\ \ | | | | | | | Add "write_verilog -siminit" | ||||
| | * | | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 2 | -3/+12 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 9 | -29/+29 |
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| * | | Fix pmgen for in-tree builds | Clifford Wolf | 2019-02-28 | 2 | -8/+9 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 7 | -12/+388 |
| |\ \ | | | | | | | ECP5 Improvements | ||||
| | * | | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 2 | -0/+20 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | | ecp5: Add DDRDLLA | David Shah | 2019-02-19 | 1 | -0/+9 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | | ecp5: Add DELAYF/DELAYG blackboxes | David Shah | 2019-02-19 | 1 | -0/+18 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | | ecp5: Add ECLKSYNCB blackbox | David Shah | 2019-02-13 | 1 | -1/+7 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 4 | -11/+21 |
| |\ \ \ | |_|/ |/| | | Fix FIRRTL to Verilog process instance subfield assignment. | ||||
| | * | | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 4 | -11/+21 |
| | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | ||||
| * | | | Fix pmgen for out-of-tree build | Clifford Wolf | 2019-02-28 | 2 | -4/+6 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #833 from YosysHQ/clifford/fix831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 |
| |\ \ \ | | | | | | | | | Fix smt2 code generation for partially initialized memory words, fixe… | ||||
| | * | | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #832 from YosysHQ/supercover | Clifford Wolf | 2019-02-28 | 2 | -0/+93 |
| |\ \ \ | | | | | | | | | Add "supercover" pass | ||||
| | * | | | Improvements in "supercover" pass | Clifford Wolf | 2019-02-27 | 1 | -2/+18 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add "supercover" skeleton | Clifford Wolf | 2019-02-27 | 2 | -0/+77 |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 |
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| * | | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 3 | -6/+6 |
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| * | | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant ↵ | Clifford Wolf | 2019-02-24 | 1 | -5/+1 |
| | | | | | | | | | | | | | to -check Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #812 from ucb-bar/arrayhierarchyfixes | Clifford Wolf | 2019-02-24 | 3 | -11/+108 |
| |\ \ | | | | | | | Define basic_cell_type() function and use it to derive the cell type … | ||||
| | * | | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 3 | -11/+14 |
| | | | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. | ||||
| | * | | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 3 | -10/+74 |
| | | | | | | | | | | | | | Add simple test. | ||||
| | * | | Define basic_cell_type() function and use it to derive the cell type for ↵ | Jim Lawson | 2019-02-15 | 1 | -10/+40 |
| | | | | | | | | | | | | | array references (instead of duplicating the code). | ||||
| * | | | Cleanups in ARST handling in wreduce | Clifford Wolf | 2019-02-24 | 1 | -10/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #824 from litghost/fix_reduce_on_ff | Clifford Wolf | 2019-02-24 | 3 | -0/+37 |
| |\ \ \ | | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | ||||
| | * | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | Keith Rothman | 2019-02-22 | 3 | -0/+37 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 2 | -0/+6 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #819 from YosysHQ/clifford/optd | Clifford Wolf | 2019-02-22 | 1 | -2/+16 |
| |\ \ \ \ | | | | | | | | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | ||||
| | * | | | | Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" | Clifford Wolf | 2019-02-21 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | Clifford Wolf | 2019-02-21 | 1 | -2/+16 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Merge pull request #820 from YosysHQ/clifford/fix810 | Clifford Wolf | 2019-02-22 | 5 | -54/+26 |
| |\ \ \ \ \ | | | | | | | | | | | | | Fix #810 and fix #814 | ||||
| | * | | | | | Fix Travis | Clifford Wolf | 2019-02-22 | 3 | -42/+11 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks like that whole "Fixing Travis's git clone" code was just there to make the "git describe --tags" work. I simply removed both. Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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