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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-01 10:53:23 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-01 10:53:23 -0800 |
| commit | 66fd6396d4795ea9559cbbd1560387e7d7e79596 (patch) | |
| tree | eec885cceb81e9cb57d62ad5b8333f0b6f4f56b6 | |
| parent | 60e3c38054f10251021fa2f504ad2424da33aa1d (diff) | |
| parent | ca2b3feed82f923f06d0cf57787818f0f6793157 (diff) | |
| download | yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.tar.gz yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.tar.bz2 yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.zip | |
Merge pull request #841 from mmicko/master
Fix ECP5 cells_sim for iverilog
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 8320ee70a..1e4002ee0 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + wire srval; generate if (LSRMODE == "PRLD") - wire srval = M; + assign srval = M; else - localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0; + assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; endgenerate initial Q = srval; |