| Commit message (Expand) | Author | Age | Files | Lines | ||
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| ... | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | Check abc_box_id attr | Eddie Hung | 2019-04-15 | 1 | -1/+16 | |
| | * | | | | | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 9 | -100/+246 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | PI before CI | Eddie Hung | 2019-04-12 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 1 | -1/+0 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 6 | -8/+93 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -24/+21 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-lut <file>" support to abc9 | Eddie Hung | 2019-04-09 | 1 | -13/+31 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "-box" option to abc9 | Eddie Hung | 2019-04-09 | 1 | -7/+22 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'setundef -zero' call prior to aigmap in abc9 | Eddie Hung | 2019-04-09 | 1 | -0/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Comment out | Eddie Hung | 2019-04-09 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 2 | -1/+14 | |
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 140 | -1863/+4709 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | / / | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1082 from corecode/u4k | David Shah | 2019-06-10 | 1 | -0/+24 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 | |
| | |/ / / / / / / / / / / / / / / / / / / / / / / / / / | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs | Clifford Wolf | 2019-06-08 | 1 | -12/+42 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 | |
| | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger | Clifford Wolf | 2019-06-07 | 27 | -45/+128 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Add read_aiger to CHANGELOG | Eddie Hung | 2019-06-07 | 1 | -0/+1 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 | |
| | |/ / / / / / / / / / / / / / / / / / / / / / / / / | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 | |
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index : iCE40/yosys | |
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