iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #893 from YosysHQ/clifford/btormeminit	Clifford Wolf	2019-03-23	3	-3/+63
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\| *	Add support for memory initialization to write_btor	Clifford Wolf	2019-03-23	1	-0/+53
\| *	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
\| *	Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals	Clifford Wolf	2019-03-23	2	-1/+9
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*	Merge pull request #889 from YosysHQ/clifford/fix888	Clifford Wolf	2019-03-22	1	-1/+10
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\| *	Fix mem2reg handling of memories with upto data ports, fixes #888	Clifford Wolf	2019-03-21	1	-1/+10
* \|	Merge pull request #890 from YosysHQ/clifford/fix887	Clifford Wolf	2019-03-22	1	-1/+26
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\| * \|	Trim init attributes when resizing FFs in "wreduce", fixes #887	Clifford Wolf	2019-03-22	1	-1/+26
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* \|	Merge pull request #891 from YosysHQ/xilinx_keep	David Shah	2019-03-22	2	-25/+31
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\| *	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
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*	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
*	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	3	-15/+42
*	Merge pull request #885 from YosysHQ/clifford/fix873	Clifford Wolf	2019-03-19	1	-2/+4
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\| *	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
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*	Merge pull request #808 from eddiehung/read_aiger	Eddie Hung	2019-03-19	35	-6/+632
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\| *	Merge https://github.com/YosysHQ/yosys into read_aiger	Eddie Hung	2019-03-19	113	-792/+6364
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* \|	Merge pull request #884 from zachjs/master	Clifford Wolf	2019-03-19	2	-1/+61
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\| * \|	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	2	-1/+61
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* \|	Update issue template	Clifford Wolf	2019-03-17	1	-5/+5
* \|	Update issue template	Clifford Wolf	2019-03-17	1	-0/+8
* \|	Merge pull request #877 from FelixVi/master	Clifford Wolf	2019-03-16	1	-1/+4
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\| * \|	Add note about test requirements in README	Felix Vietmeyer	2019-03-16	1	-1/+4
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* \|	Improve mix of src/wire/wirebit coverage in "mutate -list"	Clifford Wolf	2019-03-16	1	-29/+84
* \|	Merge pull request #876 from YosysHQ/clifford/fmcombine	Clifford Wolf	2019-03-16	4	-17/+374
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\| * \|	Add "fmcombine -fwd -bwd -nop"	Clifford Wolf	2019-03-15	1	-10/+59
\| * \|	Add fmcombine pass	Clifford Wolf	2019-03-15	4	-17/+325
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* \|	Merge pull request #875 from YosysHQ/clifford/mutate	Clifford Wolf	2019-03-15	4	-5/+862
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\| * \|	Improvements in "mutate" list-reduce algorithm	Clifford Wolf	2019-03-15	1	-13/+36
\| * \|	Add "mutate -cfg", improve pick_cover behavior	Clifford Wolf	2019-03-14	1	-46/+101
\| * \|	Add a strictly coverage-driven mutation selection strategy	Clifford Wolf	2019-03-14	1	-1/+70
\| * \|	Improve "mutate" wire coverage metric	Clifford Wolf	2019-03-14	1	-1/+16
\| * \|	Add more mutation types, improve mutation src cover	Clifford Wolf	2019-03-14	1	-92/+268
\| * \|	Fix smtbmc.py handling of zero appended steps	Clifford Wolf	2019-03-14	1	-5/+5
\| * \|	Add "mutate" command DB reduce functionality	Clifford Wolf	2019-03-14	1	-12/+181
\| * \|	Add hashlib "<container>::element(int n)" methods	Clifford Wolf	2019-03-14	1	-0/+6
\| * \|	Add "mutate -mode inv", various other mutate improvements	Clifford Wolf	2019-03-14	1	-99/+213
\| * \|	Add basic "mutate -list N" framework	Clifford Wolf	2019-03-14	2	-0/+230
* \| \|	Disable realmath tests	Clifford Wolf	2019-03-15	1	-1/+1
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* \|	Merge pull request #874 from YosysHQ/clifford/andopt	Clifford Wolf	2019-03-14	1	-0/+7
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\| * \|	Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327	Clifford Wolf	2019-03-14	1	-0/+7
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* \|	Merge pull request #872 from YosysHQ/clifford/pmuxfix	Clifford Wolf	2019-03-14	2	-1/+10
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\| * \|	Improve handling of "full_case" attributes	Clifford Wolf	2019-03-14	1	-0/+9
\| * \|	Fix a syntax bug in ilang backend related to process case statements	Clifford Wolf	2019-03-14	1	-1/+1
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* \|	Merge pull request #869 from cr1901/win-shell	Clifford Wolf	2019-03-14	3	-1/+377
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\| * \|	Install launcher executable when running yosys-smtbmc on Windows.	William D. Jones	2019-03-13	3	-1/+377
* \| \|	Merge pull request #868 from YosysHQ/clifford/fixmem	Clifford Wolf	2019-03-13	2	-40/+24
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\| * \| \|	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
\| * \| \|	Improve handling of memories used in mem index expressions on LHS of an assig...	Clifford Wolf	2019-03-12	1	-5/+16
\| * \| \|	Remove outdated "blocking assignment to memory" warning	Clifford Wolf	2019-03-12	1	-10/+0
\| * \| \|	Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867	Clifford Wolf	2019-03-12	1	-6/+8
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