| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| | | | | | * | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
| | | | | | * | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 | |
| | | | | | * | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
| | | | | | * | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
| | | | | | * | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
| | | | | | * | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | | | * | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
| | | | | | * | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 | |
| | | | | | * | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 | |
| | | | | | * | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 | |
| | | | | | * | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 | |
| | | | | | * | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 | |
| | | | | | * | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 7 | -50/+172 | |
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| | | * | | | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 | |
| | | * | | | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 | |
| | | * | | | | Add INIT parameter to all ff/latch cells | Eddie Hung | 2019-02-06 | 2 | -43/+86 | |
| | | * | | | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 | |
| | | * | | | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 | |
| | | * | | | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 | |
| | | * | | | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 | |
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| * | | | | | Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::... | Clifford Wolf | 2019-02-06 | 1 | -1/+1 | |
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| | | | * | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 | |
| | | | * | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 | |
| | | | * | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 | |
| | | | * | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 | |
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| * | | | Merge pull request #798 from mmicko/master | Clifford Wolf | 2019-01-27 | 1 | -1/+1 | |
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| | * | | | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 | |
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| * | | | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 | |
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| | * | | | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 | |
| * | | | | Merge branch 'whitequark-write_verilog_keyword' | Clifford Wolf | 2019-01-27 | 5 | -69/+27 | |
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| | * | | | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 | |
| | * | | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 | |
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| * | | | Merge pull request #796 from whitequark/proc_clean_typo | David Shah | 2019-01-25 | 1 | -1/+1 | |
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| | * | | proc_clean: fix critical typo. | whitequark | 2019-01-23 | 1 | -1/+1 | |
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| * | | Merge pull request #793 from whitequark/proc_clean_fix_fully_def | Clifford Wolf | 2019-01-19 | 1 | -1/+7 | |
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| | * | | proc_clean: fix fully def check to consider compare/signal length. | whitequark | 2019-01-18 | 1 | -1/+7 | |
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| * | | Cleanups in igloo2 example design | Clifford Wolf | 2019-01-17 | 6 | -7/+4 | |
| * | | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 6 | -3/+171 | |
| * | | Improve Igloo2 example | Clifford Wolf | 2019-01-17 | 8 | -22/+41 | |
| * | | Add "synth_sf2 -vlog", fix "synth_sf2 -edif" | Clifford Wolf | 2019-01-17 | 1 | -2/+17 | |
| * | | Add "write_edif -gndvccy" | Clifford Wolf | 2019-01-17 | 1 | -5/+13 | |
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| * | Add optional nullstr argument to log_id() | Clifford Wolf | 2019-01-15 | 1 | -1/+3 | |
| * | Fix handling of $shiftx in Verilog back-end | Clifford Wolf | 2019-01-15 | 1 | -3/+6 | |
| * | Merge pull request #788 from whitequark/master | Clifford Wolf | 2019-01-15 | 1 | -5/+17 | |
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| | * | manual: document some gates. | whitequark | 2019-01-14 | 1 | -9/+11 | |
| | * | manual: explain $tribuf cell. | whitequark | 2019-01-14 | 1 | -0/+10 | |
| * | | Merge pull request #787 from whitequark/flowmap_relax | Clifford Wolf | 2019-01-15 | 7 | -35/+776 | |
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| | * | flowmap: clean up terminology. | whitequark | 2019-01-08 | 1 | -17/+18 | |
| | * | flowmap: implement depth relaxation. | whitequark | 2019-01-08 | 7 | -22/+762 | |
| * | | Improve igloo2 example | Clifford Wolf | 2019-01-08 | 4 | -5/+29 | |
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index : iCE40/yosys | |
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