aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | | | | | | | | | | xilinx_srl to support FDRE and FDRE_1Eddie Hung2019-08-212-10/+73
| * | | | | | | | | | | | | Fix polarity of EN_POLEddie Hung2019-08-211-2/+2
| * | | | | | | | | | | | | Add CLKPOL == 0Eddie Hung2019-08-211-0/+2
| * | | | | | | | | | | | | Reject if not minlen from inside pattern matcherEddie Hung2019-08-212-8/+11
| * | | | | | | | | | | | | Get wire via SigBitEddie Hung2019-08-211-4/+4
| * | | | | | | | | | | | | Respect \keep on cells or wiresEddie Hung2019-08-211-2/+10
| * | | | | | | | | | | | | Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srlEddie Hung2019-08-212-0/+17
| |\ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | Add init supportEddie Hung2019-08-212-3/+12
| * | | | | | | | | | | | | | Fix spacingEddie Hung2019-08-211-2/+2
| * | | | | | | | | | | | | | Initial progress on xilinx_srlEddie Hung2019-08-213-0/+213
* | | | | | | | | | | | | | | Format `-pwires`Eddie Hung2019-08-301-1/+1
| |_|_|_|_|_|_|_|/ / / / / / |/| | | | | | | | | | | | |
* | | | | | | | | | | | | | Merge pull request #1343 from whitequark/diamond-ffsDavid Shah2019-08-307-106/+147
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | |
| * | | | | | | | | | | | | ecp5: Add simulation equivalence check for Diamond FF implementationsDavid Shah2019-08-303-0/+87
| * | | | | | | | | | | | | ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.whitequark2019-08-305-95/+60
| * | | | | | | | | | | | | ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.whitequark2019-08-301-35/+20
| * | | | | | | | | | | | | ecp5: add missing FD primitives.whitequark2019-08-302-72/+76
| * | | | | | | | | | | | | ecp5: fix CEMUX on IFS/OFS primitives.whitequark2019-08-302-18/+18
|/ / / / / / / / / / / / /
* | | | | | | | | | | | | Merge pull request #1337 from YosysHQ/eddie/fix_carry_wrapperEddie Hung2019-08-297-27/+71
|\ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | |
| * | | | | | | | | | | | Rename boxes tooEddie Hung2019-08-293-3/+3
| * | | | | | | | | | | | Add run-test.sh tooEddie Hung2019-08-281-0/+20
| * | | | | | | | | | | | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
| * | | | | | | | | | | | Add SB_CARRY to ice40_opt testEddie Hung2019-08-281-3/+5
| * | | | | | | | | | | | Add ice40_opt testEddie Hung2019-08-281-0/+24
| * | | | | | | | | | | | Trailing commaEddie Hung2019-08-281-1/+1
| * | | | | | | | | | | | Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
| * | | | | | | | | | | | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
| * | | | | | | | | | | | Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| * | | | | | | | | | | | Update box size and timingsEddie Hung2019-08-283-12/+12
| * | | | | | | | | | | | Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
* | | | | | | | | | | | | Fix typo that's gone unnoticed for 5 months!?!Eddie Hung2019-08-291-1/+1
* | | | | | | | | | | | | Bump YOSYS_VERClifford Wolf2019-08-291-1/+1
|/ / / / / / / / / / / /
| | | | | | | | | | | * Add constant expression attribute to testEddie Hung2019-08-291-0/+1
| | | | | | | | | | | * Remove newlineEddie Hung2019-08-291-1/+0
| | | | | | | | | | | * Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
| | | | | | | | | | | * -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
| | | | | | | | | | | * read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
| | | | | | | | | | | * Add failing testEddie Hung2019-08-281-0/+18
| |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | |
* | | | | | | | | | | Merge pull request #1334 from YosysHQ/clifford/async2synclatchEddie Hung2019-08-281-1/+36
|\ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|/ | |/| | | | | | | | |
| * | | | | | | | | | Add $dlatch support to async2syncClifford Wolf2019-08-281-1/+36
* | | | | | | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
| |_|_|_|_|_|_|_|/ / |/| | | | | | | | |
* | | | | | | | | | Merge pull request #1332 from YosysHQ/dave/ecp5gsrDavid Shah2019-08-286-54/+212
|\ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | ecp5: Add GSR supportDavid Shah2019-08-276-54/+212
* | | | | | | | | | | Merge pull request #1335 from YosysHQ/clifford/paramapClifford Wolf2019-08-281-68/+119
|\ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / |/| | | | | | | | | |
| * | | | | | | | | | Fix typoClifford Wolf2019-08-281-2/+2
| * | | | | | | | | | Add "paramap" passClifford Wolf2019-08-281-67/+118
|/ / / / / / / / / /
* | | | | | | | | | Merge pull request #1325 from YosysHQ/eddie/sat_initClifford Wolf2019-08-282-2/+8
|\ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | Ignore all 1'bx in (* init *)Eddie Hung2019-08-271-3/+1
| * | | | | | | | | | Revert to using cleanEddie Hung2019-08-271-1/+1
| * | | | | | | | | | Wire with init on FF part, 1'bx on non-FF partEddie Hung2019-08-241-1/+3
| * | | | | | | | | | Blocking assignmentEddie Hung2019-08-231-1/+1