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| * | | | | | | | | | | | Add abc9.v testcase to simple_abc9 | Eddie Hung | 2019-02-21 | 1 | -4/+46 |
| * | | | | | | | | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-21 | 2 | -27/+7 |
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| | * | | | | | | | | | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 | Clifford Wolf | 2019-02-21 | 1 | -6/+7 |
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| | * | | | | / / / / | Merge pull request #817 from eddiehung/dff_init | Eddie Hung | 2019-02-20 | 1 | -21/+0 |
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| | | * | | | | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 |
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| * | | | | | | | | ABC -> ABC9 | Eddie Hung | 2019-02-20 | 1 | -1/+1 |
| * | | | | | | | | abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ | Eddie Hung | 2019-02-20 | 1 | -21/+29 |
| * | | | | | | | | read_aiger to not do -purge for clean | Eddie Hung | 2019-02-20 | 1 | -1/+1 |
| * | | | | | | | | lut/not/and suffix to be ${lut,not,and} | Eddie Hung | 2019-02-20 | 2 | -17/+17 |
| * | | | | | | | | simple_abc9 tests to now preserve memories | Eddie Hung | 2019-02-20 | 1 | -1/+1 |
| * | | | | | | | | read_aiger to also rename 0 index lut when wideports | Eddie Hung | 2019-02-20 | 1 | -2/+14 |
| * | | | | | | | | Remove swap file | Eddie Hung | 2019-02-20 | 1 | -0/+0 |
| * | | | | | | | | write_aiger: fix CI/CO and symbols | Eddie Hung | 2019-02-20 | 2 | -7/+13 |
| * | | | | | | | | Move tests/techmap/abc9 to simple_abc9 | Eddie Hung | 2019-02-20 | 4 | -23/+0 |
| * | | | | | | | | Add tests/simple_abc9 | Eddie Hung | 2019-02-20 | 1 | -0/+23 |
| * | | | | | | | | abc9 to cope with multiple modules | Eddie Hung | 2019-02-20 | 1 | -7/+11 |
| * | | | | | | | | abc9 to use & syntax for -fast, and name fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 |
| * | | | | | | | | read_aiger: new naming fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 |
| * | | | | | | | | read_aiger to name wires with internal name, less likely to clash | Eddie Hung | 2019-02-20 | 1 | -18/+15 |
| * | | | | | | | | write_xaiger to not write latches, CO/PO fixes | Eddie Hung | 2019-02-20 | 1 | -17/+26 |
| * | | | | | | | | synth to take -abc9 argument | Eddie Hung | 2019-02-20 | 1 | -5/+13 |
| * | | | | | | | | abc9 to cope with indexed wires when creating $lut from $_NOT_ | Eddie Hung | 2019-02-19 | 1 | -1/+6 |
| * | | | | | | | | Add a quick abc9 test | Eddie Hung | 2019-02-19 | 4 | -0/+29 |
| * | | | | | | | | Same for ascii AIGERs too | Eddie Hung | 2019-02-19 | 1 | -6/+13 |
| * | | | | | | | | read_aiger to cope with non-unique POs | Eddie Hung | 2019-02-19 | 1 | -6/+13 |
| * | | | | | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 9 | -160/+353 |
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| | * | | | | | | | Merge pull request #805 from eddiehung/dff_init | Eddie Hung | 2019-02-19 | 4 | -2/+76 |
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| | | * | | | | | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 |
| | | * | | | | | Revert "Add INIT parameter to all ff/latch cells" | Eddie Hung | 2019-02-17 | 2 | -86/+43 |
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| | | * | | | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 9 | -100/+345 |
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| | * | | | | | Merge pull request #811 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-17 | 6 | -56/+298 |
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| | | * | | | | | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 |
| | | * | | | | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 |
| | | * | | | | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 5 | -55/+317 |
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| * | | | | | | abc9 to replace $_NOT_ with $lut | Eddie Hung | 2019-02-19 | 1 | -4/+39 |
| * | | | | | | read_aiger to create sane $lut names, and rename when renaming driving wire | Eddie Hung | 2019-02-19 | 1 | -2/+11 |
| * | | | | | | Add comment | Eddie Hung | 2019-02-19 | 1 | -1/+2 |
| * | | | | | | Get rid of boost dep, fix the FIXMEs for Win32? | Eddie Hung | 2019-02-19 | 1 | -14/+14 |
| * | | | | | | Get rid of debugging stuff in abc9 | Eddie Hung | 2019-02-16 | 1 | -6/+1 |
| * | | | | | | In read_xaiger, do not construct ConstEval for every LUT | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
| * | | | | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -4/+5 |
| * | | | | | | read_aiger to ignore output = input of same wire; also create new output for ... | Eddie Hung | 2019-02-16 | 1 | -2/+16 |
| * | | | | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -2/+1 |
| * | | | | | | write_xaiger to support non-bit cell connections, and cope with COs for -O | Eddie Hung | 2019-02-16 | 1 | -13/+15 |
| * | | | | | | abc9 to write_aiger with -O option, and ignore dummy outputs | Eddie Hung | 2019-02-16 | 1 | -2/+8 |
| * | | | | | | write_aiger -O to write dummy output as __dummy_o__ | Eddie Hung | 2019-02-16 | 1 | -2/+5 |
| * | | | | | | abc9 to handle comb loops, cope with constant outputs, disconnect using new wire | Eddie Hung | 2019-02-16 | 1 | -4/+67 |
| * | | | | | | read_aiger to disable log_debug | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
| * | | | | | | expose command to not skip 'internal' wires beginning with '$' | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
| * | | | | | | read_xaiger() to use f.read() not readsome() | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
