| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | | | Renaming BRAM memory tests for the sake of uniformity | Diego H | 2019-12-13 | 2 | -6/+6 | |
| | | * | | | | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 2 | -7/+7 | |
| | | * | | | | | | Adding a note (TODO) in the memory_params.ys check file | Diego H | 2019-12-12 | 1 | -0/+2 | |
| | | * | | | | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 3 | -2/+92 | |
| | | * | | | | | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 43 | -1053/+2108 | |
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| | | * | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
| * | | | | | | | | Bump ABC again | Eddie Hung | 2019-12-18 | 1 | -1/+1 | |
| * | | | | | | | | Remove &verify -s | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| * | | | | | | | | Bump ABC for upstream fix | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| * | | | | | | | | Use pool<> instead of std::set<> to preserver ordering | Eddie Hung | 2019-12-17 | 1 | -6/+6 | |
| * | | | | | | | | aiger frontend to user shorter, $-prefixed, names | Eddie Hung | 2019-12-17 | 1 | -14/+14 | |
| * | | | | | | | | Cleanup xaiger, remove unnecessary complexity with inout | Eddie Hung | 2019-12-17 | 2 | -84/+24 | |
| * | | | | | | | | read_xaiger to cope with optional '\n' after 'c' | Eddie Hung | 2019-12-17 | 1 | -2/+2 | |
| * | | | | | | | | Do not sigmap | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| * | | | | | | | | Revert "Use sigmap signal" | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| * | | | | | | | | abc9 needs a clean afterwards | Eddie Hung | 2019-12-16 | 1 | -2/+4 | |
| * | | | | | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 | |
| * | | | | | | | | Use sigmap signal | Eddie Hung | 2019-12-16 | 1 | -1/+1 | |
| * | | | | | | | | Skip $inout transformation if not a PI | Eddie Hung | 2019-12-16 | 1 | -3/+5 | |
| * | | | | | | | | Revert "write_xaiger: use sigmap bits more consistently" | Eddie Hung | 2019-12-16 | 1 | -4/+5 | |
| * | | | | | | | | write_xaiger: use sigmap bits more consistently | Eddie Hung | 2019-12-16 | 1 | -5/+4 | |
| * | | | | | | | | Name inputs/outputs of aiger 'i%d' and 'o%d' | Eddie Hung | 2019-12-13 | 1 | -13/+6 | |
| * | | | | | | | | Remove 'clkpart' entry in CHANGELOG | Eddie Hung | 2019-12-12 | 1 | -1/+0 | |
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 18 | -64/+238 | |
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| | * | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
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| | * | | | | | | Update README.md :: abc_ -> abc9_ | Eddie Hung | 2019-12-11 | 1 | -3/+3 | |
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| | * | | | | | Fix bitwidth mismatch; suppresses iverilog warning | Eddie Hung | 2019-12-11 | 1 | -4/+4 | |
| | * | | | | | Merge pull request #1564 from ZirconiumX/intel_housekeeping | David Shah | 2019-12-11 | 8 | -6/+6 | |
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| | | * | | | | | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
| | | * | | | | | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
| | * | | | | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 8 | -51/+225 | |
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| | | * | | | | | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 | |
| | | * | | | | | ice40_wrapcarry -unwrap to preserve 'src' attribute | Eddie Hung | 2019-12-09 | 1 | -1/+9 | |
| | | * | | | | | unmap $__ICE40_CARRY_WRAPPER in test | Eddie Hung | 2019-12-09 | 1 | -1/+21 | |
| | | * | | | | | -unwrap to create $lut not SB_LUT4 for opt_lut | Eddie Hung | 2019-12-09 | 1 | -7/+5 | |
| | | * | | | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 2 | -8/+12 | |
| | | * | | | | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 4 | -39/+61 | |
| | | * | | | | | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 2 | -2/+10 | |
| | | * | | | | | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+1 | |
| | | * | | | | | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+30 | |
| | | * | | | | | Check SB_CARRY name also preserved | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
| | | * | | | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| | | * | | | | | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 | |
| | | * | | | | | ice40_wrapcarry to preserve SB_CARRY's attributes | Eddie Hung | 2019-12-03 | 1 | -0/+2 | |
| | | * | | | | | Add testcase | Eddie Hung | 2019-12-03 | 1 | -0/+60 | |
| * | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
| * | | | | | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 19 | -971/+1773 | |
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| | * | | | | | | Merge pull request #1555 from antmicro/fix-macc-xilinx-test | Eddie Hung | 2019-12-06 | 1 | -1/+1 | |
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| | | * | | | | | tests: arch: xilinx: Change order of arguments in macc.sh | Jan Kowalewski | 2019-12-06 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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