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| * | | Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| * | | Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| * | | Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
* | | | Merge pull request #3040 from YosysHQ/micko/split_module_portsClaire Xen2021-10-111-0/+2
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| * | | | Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
* | | | | Merge pull request #3041 from YosysHQ/mmicko/module_attrClaire Xen2021-10-111-0/+1
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| * | | | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* | | | Bump versiongithub-actions[bot]2021-10-091-1/+1
* | | | Fix a regression from #3035.Marcelina Kościelnicka2021-10-082-1/+22
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* | | Bump versiongithub-actions[bot]2021-10-081-1/+1
* | | FfData: some refactoring.Marcelina Kościelnicka2021-10-0714-546/+660
* | | Bump versiongithub-actions[bot]2021-10-051-1/+1
* | | verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
* | | Bump versiongithub-actions[bot]2021-10-031-1/+1
* | | Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-029-11/+77
* | | zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
* | | kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-0210-325/+565
* | | Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-029-2/+527
* | | Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
* | | simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-023-290/+26
* | | Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_constMiodrag Milanović2021-09-281-9/+13
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| * | | Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
* | | | Bump versiongithub-actions[bot]2021-09-281-1/+1
* | | | Prepare for next release cycleMiodrag Milanovic2021-09-272-3/+6
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* | | Bump versiongithub-actions[bot]2021-09-251-1/+1
* | | Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2441-79/+80
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| * | | Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
| * | | Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
* | | | Bump versiongithub-actions[bot]2021-09-221-1/+1
* | | | sv: support wand and wor of data typesZachary Snow2021-09-214-10/+53
* | | | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-214-4/+110
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* | | Bump versiongithub-actions[bot]2021-09-191-1/+1
* | | Merge pull request #3010 from the6p4c/masterMiodrag Milanović2021-09-181-0/+2
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| * | | Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
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* | | Bump versiongithub-actions[bot]2021-09-141-1/+1
* | | verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
* | | Updates for CHANGELOG (#2997)Miodrag Milanović2021-09-131-48/+126
* | | Bump versiongithub-actions[bot]2021-09-111-1/+1
* | | Merge pull request #3001 from YosysHQ/claire/sigcheckMiodrag Milanović2021-09-102-6/+14
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| * | | Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
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* | | yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
* | | Bump versiongithub-actions[bot]2021-09-101-1/+1
* | | abc9: make re-entrant (#2993)Eddie Hung2021-09-093-9/+29
* | | abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-092-1/+15
* | | abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-093-7/+30
* | | Bump versiongithub-actions[bot]2021-09-031-1/+1
* | | update required verific versionMiodrag Milanovic2021-09-021-1/+1
* | | Bump versiongithub-actions[bot]2021-09-011-1/+1
* | | sv: support declaration in generate for initializationZachary Snow2021-08-319-1/+209
* | | Bump versiongithub-actions[bot]2021-08-311-1/+1