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| author | Eddie Hung <eddie@fpgeh.com> | 2021-09-09 10:06:20 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-09 10:06:20 -0700 |
| commit | 65316ec9262e1cc10fdc7215f2d3ead579d1e258 (patch) | |
| tree | 3e91e19b89af3700b3844bb6c5d3ac4d7dcb90f0 | |
| parent | f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0 (diff) | |
| download | yosys-65316ec9262e1cc10fdc7215f2d3ead579d1e258.tar.gz yosys-65316ec9262e1cc10fdc7215f2d3ead579d1e258.tar.bz2 yosys-65316ec9262e1cc10fdc7215f2d3ead579d1e258.zip | |
abc9: holes module to instantiate cells with NEW_ID (#2992)
* Add testcase
* holes module to instantiate cells with NEW_ID
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 | ||||
| -rw-r--r-- | tests/techmap/bug2759.ys | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index c3eaa70d1..a2f1dd955 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -812,7 +812,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto &holes_cell = r.first->second; if (r.second) { if (box_module->get_bool_attribute(ID::whitebox)) { - holes_cell = holes_module->addCell(cell->name, cell->type); + holes_cell = holes_module->addCell(NEW_ID, cell->type); if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc"); diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys new file mode 100644 index 000000000..05699bef8 --- /dev/null +++ b/tests/techmap/bug2759.ys @@ -0,0 +1,14 @@ +read_verilog -specify <<EOT +(* abc9_box, whitebox *) +module box(input [1:0] i, output o); +specify +(i *> o) = 1; +endspecify +assign o = ^i; +endmodule + +module top(input [1:0] i, output o); +box i1(i, o); +endmodule +EOT +abc9 -lut 4 |