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* Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wireClifford Wolf2019-07-091-0/+3
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-093-82/+26
* Merge pull request #1154 from whitequark/manual-sync-alwaysClifford Wolf2019-07-091-2/+3
* Merge pull request #1153 from YosysHQ/dave/fix_multi_muxDavid Shah2019-07-093-3/+25
* Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...Clifford Wolf2019-07-091-0/+2
* autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-07-091-1/+1
* Merge pull request #1146 from gsomlo/gls-test-abc-extClifford Wolf2019-07-094-8/+29
* Checkout yosys-0.9-rc branch of yosys-testsEddie Hung2019-07-021-1/+1
* Add missing CHANGELOG entriesEddie Hung2019-06-281-0/+3
* Merge pull request #1139 from YosysHQ/dave/check-sim-iverilogEddie Hung2019-06-272-0/+19
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| * Add simcells.v, simlib.v, and some outputEddie Hung2019-06-271-1/+11
| * tests: Check that Icarus can parse arch sim modelsDavid Shah2019-06-262-0/+9
* | GrrEddie Hung2019-06-271-1/+1
* | CapitalisationEddie Hung2019-06-271-1/+1
* | Make CHANGELOG clearerEddie Hung2019-06-271-0/+1
* | Merge pull request #1143 from YosysHQ/clifford/fix1135Eddie Hung2019-06-274-8/+38
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| * | Add #1135 testcaseEddie Hung2019-06-272-5/+26
| * | Add "pmux2shiftx -norange", fixes #1135Clifford Wolf2019-06-272-3/+12
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* | synth_xilinx -arch -> -family, consistent with older synth_intelEddie Hung2019-06-271-7/+8
* | Merge pull request #1142 from YosysHQ/clifford/fix1132Eddie Hung2019-06-272-6/+345
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| * | Copy tests from eddie/fix1132Eddie Hung2019-06-271-0/+320
| * | Fix handling of partial covers in muxcover, fixes #1132Clifford Wolf2019-06-271-6/+25
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* | Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymuxEddie Hung2019-06-272-12/+34
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| * GrrrEddie Hung2019-06-261-2/+2
| * Fix spacingEddie Hung2019-06-261-5/+5
| * Oops. Actually use nocarry flag as spotted by @koriakinEddie Hung2019-06-261-5/+7
| * synth_ecp5 rename -nomux to -nowidelut, but preserve formerEddie Hung2019-06-261-6/+6
| * Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...Eddie Hung2019-06-261-4/+24
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| | * synth_xilinx: Add -nocarry and -nomux options.Marcin Koƛcielnicki2019-04-301-7/+26
* | | Merge pull request #1137 from mmicko/cell_sim_fixClifford Wolf2019-06-262-14/+1
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| * | | Simulation model verilog fixMiodrag Milanovic2019-06-262-14/+1
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* | | Improve opt_clean handling of unused public wiresClifford Wolf2019-06-261-2/+2
* | | Improve BTOR2 handling of undriven wiresClifford Wolf2019-06-261-3/+27
* | | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
* | | Do not clean up buffer cells with "keep" attribute, closes #1128Clifford Wolf2019-06-261-1/+1
* | | Escape scope names starting with dollar sign in smtio.pyClifford Wolf2019-06-261-1/+4
* | | Add more ECP5 Diamond flip-flops.whitequark2019-06-262-30/+91
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* | Add testcase from #335, fixed by #1130Eddie Hung2019-06-251-0/+28
* | Merge pull request #1130 from YosysHQ/eddie/fix710Clifford Wolf2019-06-253-6/+33
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| * | Fix spacingEddie Hung2019-06-251-4/+3
| * | Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
| * | Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
| * | Add testEddie Hung2019-06-242-1/+22
* | | Merge pull request #1129 from YosysHQ/eddie/ram32x1dEddie Hung2019-06-255-20/+73
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| * | | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
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* | | Merge pull request #1075 from YosysHQ/eddie/muxpackClifford Wolf2019-06-255-0/+897
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| * | | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-2215-61/+450
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| * | | Cope with $reduce_or common in caseEddie Hung2019-06-211-5/+37
| * | | Add more testsEddie Hung2019-06-212-21/+51
| * | | Fix testcaseEddie Hung2019-06-211-3/+4