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* Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-063-13/+66
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| * Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-0635-290/+787
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| * | Further improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-5/+8
| * | Improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-21/+29
| * | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| * | Silently resolve completely unused cell-vs-const driver-driver conflictsClifford Wolf2019-05-011-2/+21
| * | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
* | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-064-44/+181
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| * | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| * | Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
| * | log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
| * | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
| * | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
| * | WIP -chparam support for hierarchy when verificEddie Hung2019-05-033-19/+41
| * | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
* | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
* | | Bugfix in peepopt_shiftmul.pmgClifford Wolf2019-05-061-0/+4
* | | Merge pull request #992 from bwidawsk/bison-fixClifford Wolf2019-05-061-1/+1
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| * | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
* | | | Merge pull request #989 from YosysHQ/dave/abc_name_improveClifford Wolf2019-05-061-8/+21
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| * | | | abc: Fix handling of postfixed names (e.g. for retiming)David Shah2019-05-041-4/+4
| * | | | abc: Improve name recoveryDavid Shah2019-05-041-4/+17
* | | | | Fix bug in "expose -input"Clifford Wolf2019-05-061-1/+1
* | | | | Cleanups in opt_cleanClifford Wolf2019-05-061-47/+16
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* | | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
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| * | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
* | | | Improve opt_clean handling of unused wiresClifford Wolf2019-05-041-10/+22
* | | | Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
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* | | Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
* | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
* | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-0313-151/+509
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| * | Update pmgen documentationClifford Wolf2019-05-031-6/+18
| * | Fix typoClifford Wolf2019-05-031-1/+1
| * | Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-306-1/+86
| * | pmgen progressClifford Wolf2019-04-304-13/+27
| * | Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| * | Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmgClifford Wolf2019-04-303-4/+6
| * | Progress in shiftmul peepopt patternClifford Wolf2019-04-301-3/+51
| * | Add "peepopt" skeletonClifford Wolf2019-04-295-1/+112
| * | Add pmgen support for multiple patterns in one matcherClifford Wolf2019-04-293-130/+188
| * | Support multiple pmg files (right now just concatenated together)Clifford Wolf2019-04-291-6/+30
* | | Merge pull request #984 from YosysHQ/eddie/fix_982Clifford Wolf2019-05-031-1/+2
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| * | | Revert "synth_xilinx to call dffinit with -noreinit"Eddie Hung2019-05-031-1/+1
| * | | If init is 1'bx, do not add to dict as per @cliffordwolfEddie Hung2019-05-031-1/+2
| * | | Revert "dffinit -noreinit to silently continue when init value is 1'bx"Eddie Hung2019-05-031-12/+4
| * | | synth_xilinx to call dffinit with -noreinitEddie Hung2019-05-021-1/+1
| * | | dffinit -noreinit to silently continue when init value is 1'bxEddie Hung2019-05-021-4/+12
* | | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-033-0/+25
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| * | | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-012-0/+23
| * | | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
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