aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| | | | | | * | | | | | | Add new tests for Anlogic architectureSergeyDegtyar2019-09-2323-0/+536
| | | | | |/ / / / / / /
| | | | | | | * | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-186-13/+15
| | | | | | | * | | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
| | | | | | | * | | | | Split mux tests per typeMiodrag Milanovic2019-10-042-38/+36
| | | | | | | * | | | | Split latch checkMiodrag Milanovic2019-10-042-45/+24
| | | | | | | * | | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
| | | | | | | * | | | | split rest od ff'sMiodrag Milanovic2019-10-043-30/+17
| | | | | | | * | | | | Separate check for ff's typesMiodrag Milanovic2019-10-042-47/+48
| | | | | | | * | | | | Cleaned testsMiodrag Milanovic2019-10-045-49/+4
| | | | | | | * | | | | Remove not needed testsMiodrag Milanovic2019-10-046-75/+0
| | | | | | | * | | | | Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys...Miodrag Milanovic2019-10-0431-0/+710
| |_|_|_|_|_|/| | | | | |/| | | | | | | | | | |
| | | | | | | * | | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
| | | | | | | * | | | | Merge branch 'master' into SergeyDegtyar/efinixSergey2019-10-01126-1686/+30035
| | | | | | | |\ \ \ \ \ | | | | | | | |/ / / / / | | | | | | |/| | | | |
| | | | | | | * | | | | Add new tests for Efinix architecture.SergeyDegtyar2019-09-2331-0/+710
| | | | | | |/ / / / / | | | | | |/| | | | |
* | | | | | | | | | | Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
* | | | | | | | | | | Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
* | | | | | | | | | | Bump versionClifford Wolf2019-10-031-1/+1
* | | | | | | | | | | Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
|\ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | Fix for svinterfacesEddie Hung2019-09-301-2/+8
| * | | | | | | | | | | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
| | |_|_|/ / / / / / / | |/| | | | | | | | |
* | | | | | | | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
|\ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | Add quick testEddie Hung2019-09-301-0/+10
| * | | | | | | | | | | Add -select option to aigmapEddie Hung2019-09-301-6/+40
| | |_|_|_|_|/ / / / / | |/| | | | | | | | |
* | | | | | | | | | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / |/| | | | | | | | | |
| * | | | | | | | | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| * | | | | | | | | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
* | | | | | | | | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
|\ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| * | | | | | | | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | |/ / / / / / / / / | |/| | | | | | | | |
* | | | | | | | | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|/ / / / / / / |/| | | | | | | | | |
| * | | | | | | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
| * | | | | | | | | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
| * | | | | | | | | | Add testEddie Hung2019-09-301-0/+16
| * | | | | | | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
| |/ / / / / / / / /
* | | | / / / / / / log_dump() to support State enumEddie Hung2019-10-023-0/+6
| |_|_|/ / / / / / |/| | | | | | | |
* | | | | | | | | Merge pull request #1428 from YosysHQ/clifford/fixbtorClifford Wolf2019-10-021-6/+9
|\ \ \ \ \ \ \ \ \ | |_|/ / / / / / / |/| | | | | | | |
| * | | | | | | | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
|/ / / / / / / /
* | | | | | | | Merge pull request #1426 from YosysHQ/mmicko/fix_environMiodrag Milanović2019-10-011-0/+2
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | |
| * | | | | | | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
|/ / / / / / /
* / / / / / / Fix typoEddie Hung2019-09-301-1/+1
|/ / / / / /
* | | | | | Update doc for equiv_optEddie Hung2019-09-301-2/+3
* | | | | | Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-3011-0/+1767
|\ \ \ \ \ \
| * | | | | | rpc: new frontend.whitequark2019-09-309-0/+744
| * | | | | | libs: import json11.whitequark2019-09-303-0/+1023
* | | | | | | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructorsEddie Hung2019-09-301-0/+2
|\ \ \ \ \ \ \
| * | | | | | | Generate Python wrappers for inline constructorsBenedikt Tutzer2019-09-231-0/+2
* | | | | | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-304-6/+10
|\ \ \ \ \ \ \ \
| * | | | | | | | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
| * | | | | | | | Open aig frontend as binary fileMiodrag Milanovic2019-09-294-5/+5
* | | | | | | | | Bump versionClifford Wolf2019-09-301-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 07:50:44 +0000