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* Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
* Bump versiongithub-actions[bot]2021-11-061-1/+1
* Next dev cycleMiodrag Milanovic2021-11-052-2/+5
* Release version 0.11Miodrag Milanovic2021-11-052-3/+3
* Must use latest flex to generate c++17 compatible codeMiodrag Milanovic2021-11-051-2/+4
* Make it work on allMiodrag Milanovic2021-11-052-5/+5
* Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
* Add missing changelog itemMiodrag Milanovic2021-11-051-0/+1
* Update command referenceMiodrag Milanovic2021-11-051-0/+17
* Merge pull request #3067 from YosysHQ/aki/ci_updateMiodrag Milanović2021-11-054-101/+293
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| * ci: removed the old `test.yml` workflow, as it was replaced by `test-linux.ym...Aki Van Ness2021-10-311-91/+0
| * ci: expanded the macOS tests suite to cover more compilers and C++ versionsAki Van Ness2021-10-311-0/+157
| * ci: expanded the Linux test suite to cover more compilers and C++ versionsAki Van Ness2021-10-311-0/+125
| * Changed the Makefile to have an explicit `CXXSTD` parameter which allows for ...Aki Van Ness2021-10-311-10/+11
* | Removed semicolon from macroMiodrag Milanovic2021-11-051-1/+1
* | Bump versiongithub-actions[bot]2021-11-031-1/+1
* | flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
* | Bump versiongithub-actions[bot]2021-11-021-1/+1
* | Merge pull request #3068 from YosysHQ/claire/verific_cfgClaire Xen2021-11-011-2/+75
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| * | Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
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* / Bump versiongithub-actions[bot]2021-11-011-1/+1
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* Merge pull request #3066 from YosysHQ/claire/verific_gclkClaire Xen2021-10-311-12/+67
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| * Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
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* Bump versiongithub-actions[bot]2021-10-301-1/+1
* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
* Update command reference part of manualMiodrag Milanovic2021-10-291-340/+1444
* Bump versiongithub-actions[bot]2021-10-281-1/+1
* Merge pull request #3063 from YosysHQ/micko/verific_aldffMiodrag Milanović2021-10-272-8/+1
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| * Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
| * Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-272-8/+1
* | ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-272-13/+13
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* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-2712-1053/+1137
* Bump versiongithub-actions[bot]2021-10-271-1/+1
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-2515-42/+397
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-255-28/+61
* Bump versiongithub-actions[bot]2021-10-261-1/+1
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-252-1/+8
* Bump versiongithub-actions[bot]2021-10-221-1/+1
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-212-6/+8
* Merge pull request #3057 from YosysHQ/claire/verific_latchesClaire Xen2021-10-211-4/+61
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| * Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| * Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
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* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-212-63/+46
* Bump versiongithub-actions[bot]2021-10-211-1/+1
* If verific have vhdl lib it is required by other libsMiodrag Milanovic2021-10-201-0/+4
* Forgot to remove from main listMiodrag Milanovic2021-10-201-1/+1
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-203-11/+50
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