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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 13:08:08 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 13:08:08 +0200 |
| commit | bf79ff5927d3b31faf0099870445e36211878096 (patch) | |
| tree | 7065c4fb6365e7d5fe72e498427f2c57931fe07c | |
| parent | 150ce305f9d51ec92380eb544e64af3770be5bdb (diff) | |
| download | yosys-bf79ff5927d3b31faf0099870445e36211878096.tar.gz yosys-bf79ff5927d3b31faf0099870445e36211878096.tar.bz2 yosys-bf79ff5927d3b31faf0099870445e36211878096.zip | |
If verific have vhdl lib it is required by other libs
| -rw-r--r-- | Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -504,6 +504,10 @@ VERIFIC_COMPONENTS ?= verilog database util containers hier_tree ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT +else +ifneq ($(wildcard $(VERIFIC_DIR)/vhdl),) +VERIFIC_COMPONENTS += vhdl +endif endif ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1) VERIFIC_COMPONENTS += extensions |