| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 3 | -44/+47 |
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| | * | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 |
| | |\ | | | | | | | write_verilog: correctly emit asynchronous transparent ports | ||||
| | | * | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760. | ||||
| | * | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 |
| | |\ \ | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state | ||||
| | | * | | fsm_opt: Fix runtime error for FSMs without a reset state | David Shah | 2019-02-07 | 1 | -1/+2 |
| | |/ / | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Rip out some more stuff | Eddie Hung | 2019-02-13 | 1 | -36/+0 |
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| * | | | Rip out unused functions in abc9 | Eddie Hung | 2019-02-12 | 1 | -416/+61 |
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| * | | | Add support for read_aiger -wideports | Eddie Hung | 2019-02-12 | 2 | -6/+15 |
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| * | | | Add support for read_aiger -map | Eddie Hung | 2019-02-12 | 2 | -4/+82 |
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| * | | | Parse 'm' in xaiger | Eddie Hung | 2019-02-12 | 1 | -20/+57 |
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| * | | | WIP for ABC with aiger | Eddie Hung | 2019-02-12 | 1 | -130/+19 |
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| * | | | Add read_xaiger | Eddie Hung | 2019-02-11 | 2 | -27/+108 |
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| * | | | Add write_xaiger | Eddie Hung | 2019-02-11 | 2 | -21/+11 |
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| * | | | Copy backends/aiger/aiger.cc to xaiger.cc | Eddie Hung | 2019-02-08 | 1 | -0/+788 |
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| * | | | Compile abc9 | Eddie Hung | 2019-02-08 | 2 | -8/+9 |
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| * | | | Refactor kernel/cost.h definition into cost.cc | Eddie Hung | 2019-02-08 | 3 | -49/+78 |
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| * | | | Copy abc.cc to abc9.cc | Eddie Hung | 2019-02-08 | 1 | -0/+1868 |
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| * | | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 |
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| * | | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 |
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| * | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 |
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| * | | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 |
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| * | | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 |
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| * | | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 |
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| * | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 |
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| * | | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 |
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| * | | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 |
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| * | | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 |
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| * | | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 |
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| * | | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 |
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| * | | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 |
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| * | | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 |
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| * | | | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 |
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| * | | | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 |
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| * | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 7 | -50/+172 |
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| | * | | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 |
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| | * | | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 |
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| | * | | | Add INIT parameter to all ff/latch cells | Eddie Hung | 2019-02-06 | 2 | -43/+86 |
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| | * | | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 |
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| | * | | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 |
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| | * | | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 |
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| | * | | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 |
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| | * / | Add missing blackslash-to-slash convertion to smtio.py (matching ↵ | Clifford Wolf | 2019-02-06 | 1 | -1/+1 |
| | |/ | | | | | | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 |
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| * | | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 |
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| * | | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 |
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| * | | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 |
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index : iCE40/yosys | |
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