| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
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| * | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 |
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| * | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
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| * | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 |
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| | * | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 |
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| | * | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 |
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| * | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 |
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| * | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 |
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| * | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 |
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| * | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 |
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| * | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 |
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| * | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 |
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| * | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 |
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| * | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 |
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| * | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 |
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| * | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 |
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| * | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 |
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| * | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 |
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| * | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 |
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| * | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 |
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| * | | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 |
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| * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 |
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| * | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 7 | -50/+172 |
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| | * | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 |
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| | * | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 |
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| | * | Add INIT parameter to all ff/latch cells | Eddie Hung | 2019-02-06 | 2 | -43/+86 |
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| | * | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 |
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| | * | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 |
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| | * | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 |
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| | * | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 |
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| | * | Add missing blackslash-to-slash convertion to smtio.py (matching ↵ | Clifford Wolf | 2019-02-06 | 1 | -1/+1 |
| | | | | | | | | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 |
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| * | | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 |
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| * | | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 |
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| * | | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 |
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| * | Merge pull request #798 from mmicko/master | Clifford Wolf | 2019-01-27 | 1 | -1/+1 |
| |\ | | | | | Fixed Anlogic simulation model | ||||
| | * | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 |
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| * | | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 |
| |\ \ | | | | | | | write_verilog: write $tribuf cell as ternary | ||||
| | * | | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 |
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| * | | | Merge branch 'whitequark-write_verilog_keyword' | Clifford Wolf | 2019-01-27 | 5 | -69/+27 |
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| | * | | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 |
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| * | | Merge pull request #796 from whitequark/proc_clean_typo | David Shah | 2019-01-25 | 1 | -1/+1 |
| |\ \ | |/ |/| | proc_clean: fix critical typo | ||||
| | * | proc_clean: fix critical typo. | whitequark | 2019-01-23 | 1 | -1/+1 |
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| * | Merge pull request #793 from whitequark/proc_clean_fix_fully_def | Clifford Wolf | 2019-01-19 | 1 | -1/+7 |
| |\ | | | | | proc_clean: fix fully def check to consider compare/signal length | ||||
| | * | proc_clean: fix fully def check to consider compare/signal length. | whitequark | 2019-01-18 | 1 | -1/+7 |
| |/ | | | | Fixes #790. | ||||
| * | Cleanups in igloo2 example design | Clifford Wolf | 2019-01-17 | 6 | -7/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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