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-rw-r--r--tests/various/peepopt.ys12
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 91db22423..33555264d 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -5,7 +5,7 @@ endmodule
EOT
prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$shiftx
@@ -16,16 +16,16 @@ select -assert-count 0 t:$shiftx t:* %D
design -reset
read_verilog <<EOT
module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
+assign y = 1'b1 >> (w * (8'b110));
endmodule
EOT
prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$shr
-select -assert-count 1 t:$mul
+select -assert-count 0 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
####################
@@ -40,7 +40,7 @@ endmodule
EOT
prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:*
@@ -55,7 +55,7 @@ endmodule
EOT
prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$dff r:WIDTH=2 %i