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-rw-r--r--tests/simple/dff_init.v12
-rw-r--r--tests/simple/forloops.v25
-rw-r--r--tests/simple/localparam_attr.v11
-rw-r--r--tests/simple/mem2reg.v22
-rw-r--r--tests/simple/param_attr.v11
-rw-r--r--tests/simple/peepopt.v9
-rwxr-xr-xtests/svinterfaces/runone.sh8
-rwxr-xr-xtests/tools/autotest.sh3
-rw-r--r--tests/various/chparam.sh52
-rw-r--r--tests/various/specify.v30
-rw-r--r--tests/various/specify.ys56
11 files changed, 234 insertions, 5 deletions
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index be947042e..375ea5c4d 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
+
+module dff_test_997 (y, clk, wire4);
+// https://github.com/YosysHQ/yosys/issues/997
+ output wire [1:0] y;
+ input clk;
+ input signed wire4;
+ reg [1:0] reg10 = 0;
+ always @(posedge clk) begin
+ reg10 <= wire4;
+ end
+ assign y = reg10;
+endmodule
diff --git a/tests/simple/forloops.v b/tests/simple/forloops.v
new file mode 100644
index 000000000..8665222d8
--- /dev/null
+++ b/tests/simple/forloops.v
@@ -0,0 +1,25 @@
+module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
+ integer k;
+ always @(posedge clk) begin
+ for (k=0; k<2; k=k+1)
+ p[2*k +: 2] = {a, b} ^ {2{k}};
+ x <= k + {a, b};
+ end
+ always @* begin
+ for (k=0; k<4; k=k+1)
+ q[k] = {~a, ~b, a, b} >> k[1:0];
+ y = k - {a, b};
+ end
+endmodule
+
+module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
+ integer k;
+ always @* begin
+ for (k=0; k<4; k=k+1)
+ q[k] = {~a, ~b, a, b} >> k[1:0];
+ end
+ always @* begin
+ x = k + {a, b};
+ end
+ assign y = k - {a, b};
+endmodule
diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v
new file mode 100644
index 000000000..2ef76c71c
--- /dev/null
+++ b/tests/simple/localparam_attr.v
@@ -0,0 +1,11 @@
+module uut_localparam_attr (I, O);
+
+(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
+localparam WIDTH = 1;
+
+input wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 9839fd4a8..100426785 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
assign out = bar[foo[0]];
endmodule
+// ------------------------------------------------------
+
+module mem2reg_test6 (din, dout);
+ input wire [3:0] din;
+ output reg [3:0] dout;
+
+ reg [1:0] din_array [1:0];
+ reg [1:0] dout_array [1:0];
+
+ always @* begin
+ din_array[0] = din[0 +: 2];
+ din_array[1] = din[2 +: 2];
+
+ dout_array[0] = din_array[0];
+ dout_array[1] = din_array[1];
+
+ {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
+
+ dout[0 +: 2] = dout_array[0];
+ dout[2 +: 2] = dout_array[1];
+ end
+endmodule
diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v
new file mode 100644
index 000000000..34d63a34e
--- /dev/null
+++ b/tests/simple/param_attr.v
@@ -0,0 +1,11 @@
+module uut_param_attr (I, O);
+
+(* PARAMETER_ATTRIBUTE = "attribute_content" *)
+parameter WIDTH = 1;
+
+input wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
new file mode 100644
index 000000000..b27b9fe57
--- /dev/null
+++ b/tests/simple/peepopt.v
@@ -0,0 +1,9 @@
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 0adecc797..54cf5f2ec 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -11,12 +11,12 @@ echo "" > $STDERRFILE
echo -n "Test: ${TESTNAME} -> "
-$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
-$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
+set -e
-rm -f a.out reference_result.txt dut_result.txt
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
-set -e
+rm -f a.out reference_result.txt dut_result.txt
iverilog -g2012 ${TESTNAME}_syn.v
iverilog -g2012 ${TESTNAME}_ref_syn.v
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index bb9c3bfb5..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -147,7 +147,8 @@ do
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
- "$toolsdir"/../../techlibs/common/simlib.v
+ "$toolsdir"/../../techlibs/common/simlib.v \
+ "$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0
diff --git a/tests/various/chparam.sh b/tests/various/chparam.sh
new file mode 100644
index 000000000..9bb8d81db
--- /dev/null
+++ b/tests/various/chparam.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+
+trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR
+
+cat > chparam1.sv << "EOT"
+module top #(
+ parameter [31:0] X = 0
+) (
+ input [31:0] din,
+ output [31:0] dout
+);
+ assign dout = X-din;
+endmodule
+
+module top_props #(
+ parameter [31:0] X = 0
+) (
+ input [31:0] dout
+);
+ always @* assert (dout != X);
+endmodule
+
+bind top top_props #(.X(123456789)) props (.*);
+EOT
+
+cat > chparam2.sv << "EOT"
+module top #(
+ parameter [31:0] X = 0
+) (
+ input [31:0] din,
+ output [31:0] dout
+);
+ assign dout = X-din;
+ always @* assert (dout != 123456789);
+endmodule
+EOT
+
+if ../../yosys -q -p 'verific -sv chparam1.sv'; then
+ ../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+
+ ../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+fi
+../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+
+rm chparam1.sv
+rm chparam2.sv
diff --git a/tests/various/specify.v b/tests/various/specify.v
new file mode 100644
index 000000000..afc421da8
--- /dev/null
+++ b/tests/various/specify.v
@@ -0,0 +1,30 @@
+module test (
+ input EN, CLK,
+ input [3:0] D,
+ output reg [3:0] Q
+);
+ always @(posedge CLK)
+ if (EN) Q <= D;
+
+ specify
+ if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+ $setup(D, posedge CLK &&& EN, 5);
+ $hold(posedge CLK, D &&& EN, 6);
+ endspecify
+endmodule
+
+module test2 (
+ input A, B,
+ output Q
+);
+ xor (Q, A, B);
+ specify
+ //specparam T_rise = 1;
+ //specparam T_fall = 2;
+ `define T_rise 1
+ `define T_fall 2
+ (A => Q) = (`T_rise,`T_fall);
+ //(B => Q) = (`T_rise+`T_fall)/2.0;
+ (B => Q) = 1.5;
+ endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
new file mode 100644
index 000000000..a5ca07219
--- /dev/null
+++ b/tests/various/specify.ys
@@ -0,0 +1,56 @@
+read_verilog -specify specify.v
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 2
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+cd
+write_verilog specify.out
+design -stash gold
+
+read_verilog -specify specify.out
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 2
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+cd
+design -stash gate
+
+design -copy-from gold -as gold test
+design -copy-from gate -as gate test
+rename -hide
+rename -enumerate -pattern A_% t:$specify3
+rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
+rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+select n:C_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset
+
+design -copy-from gold -as gold test2
+design -copy-from gate -as gate test2
+rename -hide
+rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
+rename -enumerate -pattern B_% t:$specify2 n:A_* %d
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-21 17:51:31 +0000