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Diffstat (limited to 'tests/xilinx/dffs.ys')
| -rw-r--r-- | tests/xilinx/dffs.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys new file mode 100644 index 000000000..f1716dabb --- /dev/null +++ b/tests/xilinx/dffs.ys @@ -0,0 +1,25 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE + +select -assert-none t:BUFG t:FDRE %% t:* %D + + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE + +select -assert-none t:BUFG t:FDRE %% t:* %D + |