diff options
Diffstat (limited to 'tests/xilinx/adffs.ys')
| -rw-r--r-- | tests/xilinx/adffs.ys | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 961e08ae9..7edab67c7 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,14 +1,44 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-none t:BUFG t:FDCE %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDCE select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT1 -select -assert-count 2 t:LUT2 -select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
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