diff options
Diffstat (limited to 'tests/verilog/func_arg_mismatch_3.ys')
| -rw-r--r-- | tests/verilog/func_arg_mismatch_3.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/verilog/func_arg_mismatch_3.ys b/tests/verilog/func_arg_mismatch_3.ys new file mode 100644 index 000000000..892824c09 --- /dev/null +++ b/tests/verilog/func_arg_mismatch_3.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [1:0] inp; + integer inp; + f = inp; + endfunction + integer x, y; + initial x = f(y); +endmodule +EOT |