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-rw-r--r--tests/various/port_sign_extend.ys13
1 files changed, 10 insertions, 3 deletions
diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys
index 0a6a93810..6d1adf7f3 100644
--- a/tests/various/port_sign_extend.ys
+++ b/tests/various/port_sign_extend.ys
@@ -1,22 +1,29 @@
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
hierarchy
flatten
+proc
+memory
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
flatten
+proc
+memory
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
hierarchy
+proc
+memory
equiv_make ref act equiv
prep -flatten -top equiv
+equiv_induct
equiv_status -assert