4 files changed, 261 insertions, 0 deletions
diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..1eb99ec37
--- /dev/null
+++ b/tests/techmap/autopurge.ys
@@ -0,0 +1,62 @@
+# https://github.com/YosysHQ/yosys/issues/1381
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+# https://github.com/YosysHQ/yosys/issues/1391
+design -reset
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys
new file mode 100644
index 000000000..13f1a3cf3
--- /dev/null
+++ b/tests/techmap/dff2dffs.ys
@@ -0,0 +1,50 @@
+read_verilog << EOT
+module top(...);
+input clk;
+input d;
+input sr;
+output reg q0, q1, q2, q3, q4, q5;
+
+initial q0 = 1'b0;
+initial q1 = 1'b0;
+initial q2 = 1'b1;
+initial q3 = 1'b1;
+initial q4 = 1'bx;
+initial q5 = 1'bx;
+
+always @(posedge clk) begin
+	q0 <= sr ? 1'b0 : d;
+	q1 <= sr ? 1'b1 : d;
+	q2 <= sr ? 1'b0 : d;
+	q3 <= sr ? 1'b1 : d;
+	q4 <= sr ? 1'b0 : d;
+	q5 <= sr ? 1'b1 : d;
+end
+
+endmodule
+EOT
+
+proc
+simplemap
+design -save ref
+
+dff2dffs
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
+
+design -load ref
+dff2dffs -match-init
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys
new file mode 100644
index 000000000..6146f829a
--- /dev/null
+++ b/tests/techmap/extractinv.ys
@@ -0,0 +1,41 @@
+read_verilog << EOT
+
+module ff4(...);
+parameter [0:0] CLK_INV = 1'b0;
+parameter [3:0] DATA_INV = 4'b0000;
+(* invertible_pin = "CLK_INV" *)
+input clk;
+(* invertible_pin = "DATA_INV" *)
+input [3:0] d;
+output [3:0] q;
+endmodule
+
+module inv(...);
+output o;
+input i;
+endmodule
+
+module top(...);
+input d0, d1, d2, d3;
+input clk;
+output q;
+ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
+endmodule
+
+EOT
+
+extractinv -inv inv o:i
+clean
+
+select -assert-count 2 top/t:inv
+select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
+
+select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
+select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
+
+select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
+select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i
diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
new file mode 100644
index 000000000..89afaafb5
--- /dev/null
+++ b/tests/techmap/wireinit.ys
@@ -0,0 +1,108 @@
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+
+endmodule
+EOT
+design -stash map
+
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
+
+endmodule
+EOT
+design -stash map_noremove
+
+read_verilog <<EOT
+module ffbb (...);
+parameter [0:0] INIT = 1'bx;
+input D, C;
+output Q;
+endmodule
+
+module top(...);
+input clk;
+input d;
+output reg q0 = 0;
+output reg q1 = 1;
+output reg qq0 = 0;
+output reg qx;
+
+always @(posedge clk) begin
+	q0 <= d;
+	q1 <= d;
+	qq0 <= q0;
+	qx <= d;
+end
+endmodule
+EOT
+
+design -save ref
+
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map
+clean
+# Make sure the parameter was used properly.
+select -assert-count 3 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are dropped from the wires iff mapping was performed.
+select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 0 top/w:qq0 a:init %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
+
+design -load ref
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map_noremove
+clean
+# Make sure the parameter was used properly.
+select -assert-count 3 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are not dropped from the wires.
+select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:qq0 a:init=1'b0 %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i