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-rw-r--r--tests/simple/arrays02.sv16
-rw-r--r--tests/simple/attrib01_module.v21
-rw-r--r--tests/simple/attrib02_port_decl.v25
-rw-r--r--tests/simple/attrib03_parameter.v28
-rw-r--r--tests/simple/attrib04_net_var.v32
-rw-r--r--tests/simple/attrib05_port_conn.v.DISABLED21
-rw-r--r--tests/simple/attrib06_operator_suffix.v23
-rw-r--r--tests/simple/attrib07_func_call.v.DISABLED21
-rw-r--r--tests/simple/attrib08_mod_inst.v22
-rw-r--r--tests/simple/attrib09_case.v26
-rw-r--r--tests/simple/defvalue.sv22
-rw-r--r--tests/simple/generate.v11
-rw-r--r--tests/simple/implicit_ports.v16
-rwxr-xr-xtests/simple/run-test.sh3
14 files changed, 286 insertions, 1 deletions
diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv
new file mode 100644
index 000000000..76c2a7388
--- /dev/null
+++ b/tests/simple/arrays02.sv
@@ -0,0 +1,16 @@
+module uut_arrays02(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [16];
+
+always @(posedge clock) begin
+ if (we)
+ memory[addr] <= wr_data;
+ rd_data <= memory[addr];
+end
+
+endmodule
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
new file mode 100644
index 000000000..adef34f5b
--- /dev/null
+++ b/tests/simple/attrib01_module.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
new file mode 100644
index 000000000..3505e7265
--- /dev/null
+++ b/tests/simple/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+ (* this_is_clock = 1 *)
+ input wire clk;
+ (* this_is_reset = 1 *)
+ input wire rst;
+ input wire inp;
+ (* an_output_register = 1*)
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ (* this_is_the_master_clock *)
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
new file mode 100644
index 000000000..562d225cd
--- /dev/null
+++ b/tests/simple/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+ (* bus_width *)
+ parameter WIDTH = 2;
+
+ (* an_attribute_on_localparam = 55 *)
+ localparam INCREMENT = 5;
+
+ input wire clk;
+ input wire rst;
+ input wire [WIDTH-1:0] inp;
+ output reg [WIDTH-1:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp;
+ output wire [7:0] out;
+
+ bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
new file mode 100644
index 000000000..8b5523406
--- /dev/null
+++ b/tests/simple/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ (* this_is_a_prescaler *)
+ reg [7:0] counter;
+
+ (* temp_wire *)
+ wire out_val;
+
+ always @(posedge clk)
+ counter <= counter + 1;
+
+ assign out_val = inp ^ counter[4];
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
new file mode 100644
index 000000000..e20e66319
--- /dev/null
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
new file mode 100644
index 000000000..e21173c58
--- /dev/null
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output reg [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
new file mode 100644
index 000000000..f55ef2316
--- /dev/null
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+ input [7:0] inp_a;
+ input [7:0] inp_b;
+
+ do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
new file mode 100644
index 000000000..c5a32234e
--- /dev/null
+++ b/tests/simple/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ (* my_module_instance = 99 *)
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
new file mode 100644
index 000000000..8551bf9d0
--- /dev/null
+++ b/tests/simple/attrib09_case.v
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output reg [1:0] out;
+
+ always @(inp)
+ (* full_case, parallel_case *)
+ case(inp)
+ 2'd0: out <= 2'd3;
+ 2'd1: out <= 2'd2;
+ 2'd2: out <= 2'd1;
+ 2'd3: out <= 2'd0;
+ endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output wire [1:0] out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv
new file mode 100644
index 000000000..b0a087ecb
--- /dev/null
+++ b/tests/simple/defvalue.sv
@@ -0,0 +1,22 @@
+module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
+ cnt #(1) foo (.clock, .cnt(cnt1), .delta);
+ cnt #(2) bar (.clock, .cnt(cnt2));
+endmodule
+
+module cnt #(
+ parameter integer initval = 0
+) (
+ input clock,
+ output logic [3:0] cnt = initval,
+`ifdef __ICARUS__
+ input [3:0] delta
+`else
+ input [3:0] delta = 10
+`endif
+);
+`ifdef __ICARUS__
+ assign (weak0, weak1) delta = 10;
+`endif
+ always @(posedge clock)
+ cnt <= cnt + delta;
+endmodule
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 3c55682cb..0e353ad9b 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -148,3 +148,14 @@ generate
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule
+
+// ------------------------------------------
+
+module gen_test6(output [3:0] o);
+generate
+ genvar i;
+ for (i = 3; i >= 0; i = i-1) begin
+ assign o[i] = 1'b0;
+ end
+endgenerate
+endmodule
diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v
new file mode 100644
index 000000000..8b0a6f386
--- /dev/null
+++ b/tests/simple/implicit_ports.v
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+ assign cout = cin;
+ assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+ wire cin = 1;
+ alu alu (
+ .a(a),
+ .b, // Implicit connection is equivalent to .b(b)
+ .cin(), // Explicitely unconnected
+ .cout(cout),
+ .result(alu_result)
+ );
+endmodule
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index aaa1cf940..967ac49f2 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then
exit 1
fi
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v
+shopt -s nullglob
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v}
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-29 00:24:09 +0000